Power-Reset Circuit With Voltage Feedback for Reliable Initialization

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Solution Overview

Problem

Conventional reset circuitry may fail to ensure reliable initialization conditions due to variances in components, allowing power to be restored to computing devices before necessary conditions are met, leading to incomplete reset operations.

Innovation Solution

A power-reset circuit comprising transistors, resistors, and a diode is used to monitor the output voltage, ensuring power is not restored until the voltage reaches a specific threshold, utilizing an RC timer to further guarantee reliable initialization by delaying power restoration until the voltage decays to a predetermined level.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional reset circuitry with RC timer is used, then the reset function is simple to implement, but the reliability of initialization conditions cannot be ensured due to component variances

Engineering Contradiction:
Improvereliability of initialization conditionsVSAvoidcomplexity of reset circuitry
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the reset circuit monitors the output voltage of the power supply circuit and compares it against a threshold voltage. The reset signal is only released when the monitored voltage confirms that initialization conditions are met, creating a closed-loop control system that ensures reliable initialization regardless of RC timer component variances.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent performs preliminary voltage monitoring and threshold comparison before releasing the reset signal. The reset circuit proactively checks whether the output voltage has reached the required level for initialization before allowing the system to proceed, ensuring that all necessary conditions are satisfied in advance.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If RC timer duration is extended to ensure initialization, then reliability of reset is improved, but the loss of time for system startup increases

Engineering Contradiction:
Improvereliability of reset operationVSAvoidstartup time of computing device
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent employs a dynamic reset release mechanism that adapts to actual system conditions. Instead of using a fixed RC timer duration, the reset circuit continuously monitors the output voltage and releases the reset signal as soon as the threshold is reached, allowing the startup time to vary dynamically based on actual initialization requirements rather than a predetermined fixed delay.

Inventive Principle:
Principle #15Dynamics

3Measurement precision

If component tolerances in RC timer are reduced to improve precision, then manufacturing cost increases, but measurement precision of reset timing is improved

Engineering Contradiction:
Improveprecision of reset timingVSAvoidease of manufacturing reset circuit
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent replaces the mechanical/electrical RC timer-based timing mechanism with an electronic voltage monitoring and threshold comparison system. Instead of relying on physical component tolerances to achieve timing precision, the system uses electronic voltage detection and comparison circuits that provide high precision without requiring tight component tolerances, thereby maintaining ease of manufacture.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10128831B1Apparatus, system, and method for ensuring reliable initialization conditions in response to external reset signals
Publication Date: 2018.11.13 JUNIPER NETWORKS INC
  • US10128831B1 patent drawing
  • US10128831B1 patent drawing
  • US10128831B1 patent drawing

AI summary

The disclosed apparatus may include (1) a first transistor whose (A) first terminal is electrically coupled to an enable node, (B) second terminal is electrically coupled to a feedback node, and (C) third terminal is electrically coupled to a ground node, (2) a second transistor whose (A) first terminal is electrically coupled to the feedback node, (B) second terminal is electrically coupled to the enable node, and (C) third terminal is electrically coupled to the ground node, (3) a resistor that is electrically coupled between the feedback node and the ground node, and (4) a diode that is electrically coupled between the feedback node and another resistor, wherein the other resistor is electrically coupled between the diode and an output-voltage node that provides electrical power to a computing device. Various other apparatuses, systems, and methods are also disclosed.