Power-On Reset Circuit for Zero Steady-State Current Detection
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Solution Overview
Problem
Conventional power-on reset (POR) circuits in integrated circuits (ICs) consume non-zero steady-state current due to low impedance paths between the supply voltage and ground, and struggle to accurately detect trigger scenarios during both ramp-up and ramp-down of the supply voltage.
Innovation Solution
The proposed POR circuit includes first and second diode circuits, first and second trip detector circuits, and a control circuit. It generates a reset signal by utilizing a trip node voltage and a reference voltage, which ramp up with the supply voltage. The control circuit adjusts the trip node voltage based on a control signal, ensuring the reset signal accurately indicates the supply voltage state without consuming non-zero steady-state current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional POR circuits use low impedance paths between supply voltage and ground to generate reset signal, then the reset signal can be generated, but non-zero steady-state current is consumed
Solution Approach 1:
The patent extracts the harmful low impedance path that causes steady-state current consumption from the conventional POR circuit. Instead of using a direct low impedance path to ground, the invention uses a capacitor to store charge during voltage ramp-up and discharge it during ramp-down, eliminating continuous current consumption while maintaining reset signal generation capability.
Solution Approach 2:
The patent implements periodic action by using a capacitor that charges during the voltage ramp-up phase and discharges during the ramp-down phase. This periodic charge-discharge cycle provides the necessary reset signal transitions without requiring continuous current flow, thereby eliminating steady-state power consumption.
2Reliability
If conventional POR circuits are designed to detect trigger scenarios, then they can respond to voltage changes, but they fail to accurately detect both ramp-up and ramp-down scenarios
Solution Approach 1:
The patent applies dynamics by making the detection mechanism adaptive to different voltage transition directions. The capacitor-based circuit naturally responds differently to rising versus falling voltages: during ramp-up, the capacitor charges and triggers reset assertion; during ramp-down, the capacitor discharges and triggers reset deassertion. This dynamic response enables accurate detection of both trigger scenarios.
Solution Approach 2:
The patent implements feedback through the capacitor voltage that reflects the supply voltage history. The capacitor voltage serves as a feedback signal that is compared against threshold levels to determine when to assert or deassert the reset signal, enabling accurate detection of both ramp-up and ramp-down trigger scenarios.
Data Source
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AI summary
A power-on reset (POR) circuit includes first and second trip detector circuits. The first trip detector circuit generates a reset signal indicative of a state of a supply voltage based on a trip node voltage that ramps up when the supply voltage ramps up. The reset signal is asserted when the trip node voltage exceeds a threshold value. The second trip detector circuit generates a control signal based on the supply voltage and a reference voltage. The reference voltage is less than the supply voltage until the supply voltage ramps down. During the ramp-down of the supply voltage, the supply voltage falls below the reference voltage, and the control signal is asserted when the supply voltage is less than the reference voltage by a different threshold value. The asserted control signal results in the trip node voltage being altered such that the reset signal is de-asserted.