Power-On Reset Circuit With Zero Standby Power
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Solution Overview
Problem
Conventional power-on reset (POR) circuits in integrated circuits generate significant power consumption due to components like reference voltage generators, comparators, and voltage dividers, affecting the performance of the entire chip.
Innovation Solution
A power-on reset system that includes a reset signal generator, a power-on reset module, and a D flip-flop, where the reset signal generator and power-on reset module are turned off after system initialization, utilizing delay units to ensure no power consumption during operation, and the D flip-flop operates without power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional POR circuit components (reference voltage generator, comparator, voltage divider) are used to detect power supply voltage and generate reset signals, then the reset function is achieved, but significant power consumption is generated affecting chip performance
Solution Approach 1:
The patent extracts and removes the power-consuming components (reference voltage generator, comparator, voltage divider) from the POR circuit, replacing them with a current mirror-based implementation that achieves the same reset function without the harmful power consumption
Solution Approach 2:
The patent changes the operating parameters of the POR circuit by using current mirrors to replicate reference currents instead of using voltage comparison, fundamentally altering how the reset detection is performed to eliminate continuous power consumption
2Reliability
If the power-on reset module operates continuously to monitor power supply voltage, then the reset function is maintained, but power consumption occurs during operation
Solution Approach 1:
The patent implements periodic action by using the power-on reset module only during the critical power-on transition phase, then turning it off once the reset condition is met, rather than maintaining continuous operation
Solution Approach 2:
The patent applies preliminary action by pre-setting the reset state through the D flip-flop and current mirror configuration during power-on, allowing the system to initialize correctly before the reset module is deactivated
Data Source
AI summary
A power-on reset system includes a reset signal generator, a power-on reset module and a D flip-flop. The reset signal generator generates a reset enable signal when powered on, and the reset enable signal is input to the power-on reset module and the D flip-flop. An output end of the power-on reset module is connected with a clock end of the D flip-flop, an output end of the D flip-flop is connected with a control end of the power-on reset module, and an output signal of the power-on reset module controls the output reset signal of the D flip-flop. When a voltage of the enable end of the power-on reset module is a high level, the power-on reset module is turned off. In such a way, the entire power-on reset system generates no power consumption, thereby improving the working performance of the entire system chip.