Power Reset Circuit Topology for Zero Standby Current
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Solution Overview
Problem
Conventional power reset circuits consume current during standby states, leading to unwanted heat generation and reduced service life of chips and batteries.
Innovation Solution
A power reset circuit design that includes a power storage unit, voltage detection units, and a switching unit to generate a reset signal based on supply voltage changes, severing the current path between the supply voltage source and ground during standby, thereby eliminating current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional power reset circuit operates in standby state to monitor supply voltage, then the chip can be reset when power supply hangs or shuts down, but the circuit consumes current during standby which generates heat and shortens service life
Solution Approach 1:
The patent extracts the harmful current consumption path from the standby operation by using a specialized transistor structure that allows the power reset circuit to monitor supply voltage without drawing continuous current. The detection function is separated from the power consumption path, enabling voltage monitoring with zero standby current.
Solution Approach 2:
The patent changes the electrical parameters of the power reset circuit by using a transistor with specific characteristics (threshold voltage, channel structure) that enable high-impedance state during normal operation. This parameter change allows the circuit to transition between active detection and zero-consumption states, resolving the contradiction between monitoring reliability and energy consumption.
2Speed
If a power reset circuit continuously monitors supply voltage to detect shutdown states, then reset signals can be generated timely, but current flows continuously causing heat generation and reduced service life
Solution Approach 1:
The patent implements periodic or event-driven monitoring rather than continuous monitoring. The power reset circuit remains in a high-impedance state and only becomes active when voltage thresholds are crossed, converting continuous operation into discrete detection events. This reduces average power consumption and heat generation while maintaining detection responsiveness.
Solution Approach 2:
The patent introduces an intermediary transistor structure that mediates between the supply voltage and the detection circuitry. This intermediary element allows voltage changes to be detected without creating a continuous current path, thereby detecting voltage drops or shutdowns while minimizing heat generation through indirect coupling.
3Reliability
If conventional power reset circuit maintains operational readiness to reset chip on power failure, then system reliability is improved, but battery service life is shortened due to continuous current draw
Solution Approach 1:
The patent extracts the current consumption from the standby monitoring function by using a transistor-based detection mechanism that draws negligible current during normal operation. The battery is disconnected from the monitoring circuit during standby, eliminating the drain on battery life while preserving the ability to detect power failures and generate reset signals when needed.
Solution Approach 2:
The power reset circuit uses the supply voltage itself as the detection signal source, requiring no additional power for monitoring. The circuit leverages the voltage being monitored to drive the detection transistors, making the monitoring function self-powered and eliminating the need for separate standby current from the battery.
Data Source
AI summary
A power reset circuit with zero standby current consumption includes a power storage unit, first, second, and third voltage detection units, a switching unit, and a power reset unit. The power storage unit stores electric power by a supply voltage source. The first, second, and third voltage detection units are connected to the supply voltage source to start a switching circuit of the first, second, and third voltage detection units in accordance with a change in a normal supply stage, a shutdown stage, and a voltage ramp-up stage of the supply voltage source, control a voltage level of the power reset unit, and thereby generate the power reset signal. Accordingly, the power reset circuit does not consume current in a standby state (the normal supply stage of the supply voltage source) and thus is characterized by zero current consumption.