Power Ring Architecture for Low-Impedance Chip Power Delivery
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Solution Overview
Problem
The increasing number of passive capacitive components in load circuits for ensuring power integrity leads to area constraints and challenges in decoupling capacitor placement, especially under heterogeneous IC integration with different frequency settings, necessitating a solution for low self-impedance without adding more components.
Innovation Solution
A power design architecture that includes a power supply circuit, power wiring, a chip, a power ring, and reference conductors disposed on a substrate, where the power ring is electrically connected to the chip and wiring, forming transmission wiring paths with designed electrical lengths to maintain low self-impedance and suppress voltage noise without using bypass capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If decoupling capacitors are added to ensure power integrity, then voltage drop problem is solved, but the number of passive capacitive components increases
Solution Approach 1:
The patent extracts the decoupling function from traditional passive capacitive components and implements it through an active circuit comprising an operational amplifier, feedback network, and associated components. This active decoupling circuit replaces multiple passive capacitors with a compact active circuit that provides equivalent or superior decoupling performance, thereby solving voltage drop while reducing component count
Solution Approach 2:
The patent substitutes passive electrical components (capacitors) with an active electronic system (operational amplifier-based circuit). This substitution transitions from a passive reactive system to an active controlled system, enabling dynamic decoupling that adapts to varying frequency requirements while occupying less board space
2Reliability
If the number of passive capacitive components increases, then power integrity is improved, but the area required for placing components increases
Solution Approach 1:
The patent merges multiple decoupling functions into a single integrated active circuit. Instead of placing multiple separate capacitors around the chip, the active decoupling circuit consolidates these functions into one compact unit, significantly reducing the area required for power integrity maintenance
3Adaptability or versatility
If different frequency settings are used under heterogeneous IC integration, then functionality is improved, but decoupling capacitor placement becomes more difficult
Solution Approach 1:
The patent implements a dynamic decoupling solution using an operational amplifier circuit that can adapt to different frequency settings. The active circuit dynamically adjusts its response based on the operating frequency, eliminating the need for fixed-frequency passive capacitors and simplifying placement in heterogeneous IC integration scenarios
Data Source
AI summary
A power design architecture including a power supply circuit, a power wiring, at least one chip, a power ring, and a first reference conductor is provided. The power wiring is connected to the power supply circuit. The power ring is disposed around the chip and electrically connected to the chip and the power wiring. The first reference conductor is electrically connected to the chip. Low self-impedance is maintained at any position of the power ring.