Peripheral Power Ring for IO State Retention in Deep Sleep
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing digital integrated circuits face challenges in reducing standby power consumption while maintaining the integrity of the operating state and minimizing burdensome trace routing requirements, particularly in system-on-a-chip (SoC) designs with deep sleep modes.
Innovation Solution
A power circuit, or power ring, is implemented along the periphery of the integrated circuit device to maintain asserted values on input/output pins during low-power sleep modes, allowing the device to detect wake-up signals and minimize signal trace routing by using a combination of powered and unpowered segments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the core of the SOC is powered down in deep sleep mode, then standby power consumption is reduced, but the IO state cannot be maintained and peripherals lose context
Solution Approach 1:
The chip is divided into multiple power domains: a special power domain (AO) that remains powered during deep sleep mode and a core power domain that can be powered down. This segmentation allows selective power management where only necessary portions of the chip remain active, reducing overall power consumption while maintaining IO state through the always-on AO domain.
Solution Approach 2:
A buffer circuit is introduced as an intermediary component between the core and the IO pads. This buffer is powered by the AO domain and maintains the IO state even when the core is powered down. The buffer acts as a mediator that preserves peripheral context without requiring the entire core to remain active.
2Reliability
If a special power domain with multiple signal routes is used to maintain IO state, then IO state can be preserved during sleep mode, but trace routing complexity increases significantly
Solution Approach 1:
Multiple control signals for different IO pads are merged into a single shared control line that originates from the AO domain. Instead of routing separate signals from the core to each pad, the invention uses one common control path that can manage multiple pads, significantly reducing the number of traces required while maintaining the ability to preserve IO state.
Solution Approach 2:
The buffer circuit designed in the AO domain serves multiple functions: it maintains IO state during deep sleep, provides wake-up detection capability, and controls multiple different pads through a universal interface. This multi-functional design reduces the need for dedicated routing for each specific function.
Data Source
AI summary
In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.