Power Semiconductor with Asymmetric Terminal Spacing
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Solution Overview
Problem
Existing power semiconductor designs face challenges in maintaining adequate insulation and creepage distances for high voltage and current applications, particularly in ensuring sufficient electrical isolation and reducing inductance.
Innovation Solution
The power semiconductor features a carrier plate with two power semiconductor components, where power terminals are arranged in a row on one side and control terminals in a row on the other side, with increased spacing between power terminals and grouped control terminals, allowing for larger cross-sectional power connections and optimized electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If power and control connections are arranged with equal distances to simplify manufacturing, then manufacturing precision is improved, but electrical insulation and creepage distances are insufficient for high voltage applications
Solution Approach 1:
The patent applies local quality by differentiating the spacing of power connections versus control connections. Power connections are arranged with larger pitch distances to ensure adequate creepage and air insulation distances for high voltage applications, while control connections can have smaller spacing. This localized differentiation of spacing quality resolves the contradiction between manufacturing simplicity and electrical insulation reliability.
2Reliability
If power connections are placed close together to reduce inductance, then electrical performance at high currents is improved, but insulation distances between power connections are reduced
Solution Approach 1:
The patent changes the geometric parameter of connection spacing by implementing a non-uniform pitch distribution. Power connections are positioned with optimized spacing that balances inductance reduction with maintaining adequate insulation distances. The connection arrangement uses varying pitch distances - smaller spacing where inductance reduction is critical and larger spacing where insulation is paramount - thereby resolving the contradiction between electrical performance and insulation requirements.
Data Source
Figure 1~2
AI summary
The invention relates to a power semiconductor with a housing and power and control connections. The power semiconductor according to the invention has a carrier plate on which at least one power semiconductor component is arranged, and a housing (1) that at least partially encloses the carrier plate with the at least one power semiconductor component. The power semiconductor component is electrically connected to power and control connections (4 to 12) that extend from the housing (1). The power connections (4, 5, 6) are arranged in a row on one side of the housing (1), and the control connections (7, 8, 9, 10, 11, 12) are arranged in a row on the other side of the housing, wherein the distance (a) between adjacent power connections (4, 5, 6) is greater than the distance (b) between adjacent control connections (7, 8, 9 and 10, 11, 12, respectively).The special arrangement of the power and control connections on both sides of the housing results in improved electrical properties, especially in applications with high voltages and currents, since the insulation distances for air and creepage distances are larger than in known power semiconductors.