Power Semiconductor Device With Fully Depleted Channel Regions
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Solution Overview
Problem
Power semiconductor devices face limitations in minimizing losses, particularly due to the lower limit of forward voltage drop in the conducting state, which restricts their efficiency in applications like power converters and electric motor driving.
Innovation Solution
A power semiconductor device configuration with spatially confined mesas and control electrodes that induce inversion channels, allowing for full depletion of channel regions, thereby reducing the load current path and minimizing losses by controlling the flow of charge carriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the channel region is made wider to reduce resistance and improve current conduction, then the conducting losses are reduced, but the device cannot achieve full depletion of the channel region, leading to higher forward voltage drop
Solution Approach 1:
The patent transitions from planar 2D channel structures to vertically oriented 3D needle-like mesas with channel regions extending in the depth direction. This dimensional change allows the channel to achieve full depletion while maintaining low resistance by increasing the effective conduction path volume without increasing the lateral footprint, thereby resolving the contradiction between reducing conducting losses and maintaining low forward voltage drop.
Solution Approach 2:
The patent changes the geometric parameters of the channel region by forming needle-like mesas with total extensions of 0.5-2.0 μm and widths of 0.05-0.2 μm. By adjusting these dimensional parameters and the doping concentration in the channel region, the device achieves optimal balance between resistance reduction and full depletion capability, resolving the contradiction between conducting losses and forward voltage drop.
2Loss of energy
If the channel region dimensions are reduced to enable full depletion, then switching losses are reduced, but the forward voltage drop increases due to higher resistance
Solution Approach 1:
The patent forms vertically oriented needle-like mesas where the channel region extends in the depth direction (0.5-2.0 μm) with narrow lateral dimensions (0.05-0.2 μm width). This vertical orientation enables full depletion of the channel while maintaining low resistance through the extended conduction path in the vertical direction, resolving the contradiction between reducing switching losses and maintaining low forward voltage drop.
Solution Approach 2:
The patent employs a composite structure combining the semiconductor substrate, drift region, and vertically oriented needle-like mesas with controlled doping profiles. This composite architecture integrates the depletion capability of narrow channels with the low resistance of extended vertical paths, simultaneously achieving reduced switching losses and low forward voltage drop.
3Ease of manufacture
If conventional planar structures are used, then manufacturing is simpler, but the device cannot achieve both low forward voltage drop and low switching losses simultaneously
Solution Approach 1:
The patent forms vertically oriented needle-like mesas extending into the drift region, creating a 3D structure from the conventional 2D planar configuration. This vertical structuring is achieved through standard semiconductor processing techniques including anisotropic etching and selective doping, making the complex 3D structure manufacturable while enabling simultaneous reduction of both forward voltage drop and switching losses.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces switching and conducting losses, enabling lower on-state voltage and improved efficiency in power semiconductor devices, particularly in high-voltage and high-current applications.
Implementation Method 1
the control electrode may be provided with a control signal having a voltage within a first range so as to induce a load current path within the channel region
Implementation Method 2
the forward voltage may induce a depletion region at a junction formed by a transition between the channel region and a drift region of the power semiconductor device
Data Source
AI summary
A power semiconductor device is disclosed. The device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure, a first cell and a second cell. A first mesa is included in the first cell, the first mesa including: a first port region and a first channel region. A second mesa included in the second cell, the second mesa including a second port region. A third cell is electrically connected to the second load terminal structure and electrically connected to a drift region. The third cell includes a third mesa comprising: a third port region, a third channel region, and a third control electrode.