Power Semiconductor Device Dynamic Avalanche Hole Management
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing power semiconductor devices, such as GTOs and IGCTs, face limitations in maximum turn-off current due to retriggering by holes reaching the cathode during dynamic avalanche, which restricts their ability to handle high voltages effectively.
Innovation Solution
A four-layer power semiconductor device with a modulated first base layer and gate base regions of varying doping densities, strategically positioned to direct holes away from the cathode and towards the gate electrode, preventing retriggering and enhancing turn-off capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If holes are collected laterally within the (p-) base layer to the gate during turn-off, then turn-off speed is improved, but holes reaching the (n+) cathode region retrigger the thyristor reducing maximum turn-off current
Solution Approach 1:
The first base layer is divided into two regions with different doping concentrations: a first region adjacent to the cathode with lower doping concentration and a second region adjacent to the gate with higher doping concentration. This local differentiation allows the first region to generate fewer carrier pairs during dynamic avalanche while the second region provides low lateral resistance for hole collection, resolving the contradiction between turn-off speed and preventing retriggering.
Solution Approach 2:
The doping concentration in the first base layer is varied spatially, being lower near the cathode and higher near the gate. This parameter change optimizes the balance between reducing carrier generation (lower doping) and improving hole collection (higher doping), thereby increasing maximum turn-off current while maintaining turn-off speed.
2Device complexity
If snubberless operation is used to limit voltage rise, then device complexity is reduced, but field distribution becomes steep generating new carrier pairs during turn-off
Solution Approach 1:
By creating a first region with lower doping concentration adjacent to the cathode, the patent locally reduces the generation of carrier pairs during dynamic avalanche in the high-field region, while the second region with higher doping concentration handles hole collection. This resolves the harmful effect of carrier pair generation in snubberless operation without adding device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device can handle significantly higher currents at high voltages without unintentional retriggering, as the modulated field distribution and doping profiles effectively manage dynamic avalanche, allowing for more robust operation in snubberless mode.
Implementation Method 1
If an IGCT is driven into this mode, holes generated at turn-off may also reach the cathode, retriggering the device and thereby limiting maximum turn- off current. The new modulation of the main blocking junction described therein influences the field distribution at high turn-off current such, that during dynamic avalanche the generated holes are located far enough from the cathode and close enough to the gate to not retrigger the device.
Implementation Method 2
The new modulation of the main blocking junction described therein influences the field distribution at high turn-off current such, that during dynamic avalanche the generated holes are located far enough from the cathode and close enough to the gate to not retrigger the device.
Data Source
Figure 1~2
Figure 3
AI summary
The power semiconductor device (1) with a four-layer npnp structure can be turned-off via a gate electrode (5). The first base layer (8) comprises a cathode base region (81) adjacent to the cathode region (6) and a gate base region (82) adjacent to the gate electrode (5), but disposed at a distance from the cathode region (6). The gate base region (82, 82') has the same nominal doping density as the cathode base region (81) in at least one first depth, the first depth being given as a perpendicular distance from the side of the cathode region (6), which is opposite the cathode metallization (2). The gate base region (82, 82') has a higher doping density than the cathode base region (81) and / or the gate base region (82) has a greater depth than the cathode base region (81) in order to modulate the field in blocking state and to defocus generated holes from the cathode when driven into dynamic avalanche.