Anticorrosive Edge Termination for Power Semiconductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Power semiconductor devices face challenges in maintaining reliable edge termination and passivation under harsh environmental conditions, particularly in traction applications where corrosion from humidity and electric fields is a concern, leading to reduced performance and reliability.
Innovation Solution
The implementation of a power semiconductor device design featuring a protection region in the edge termination region without metallic structures, unless shielded by a polysilicon layer extending at least 20 μm laterally, and the use of a hard passivation layer that does not extend above the insulation layer's lateral edge, ensuring effective voltage accommodation and preventing crevice corrosion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metallic structures are used in the edge termination region, then electrical conductivity and field screening are improved, but susceptibility to corrosion from humidity and electric fields increases
Solution Approach 1:
The patent removes metallic structures from the edge termination region entirely, extracting the harmful element (metal) that causes corrosion while maintaining device functionality through alternative means (polysilicon field rings and field plates without metal interconnects in this region).
Solution Approach 2:
The patent introduces polysilicon as an intermediary material to replace metal structures in the edge termination region. The polysilicon field rings and field plates serve as mediators that provide electrical functionality without the corrosion susceptibility of metallic structures, particularly when combined with adequate passivation layers.
2Object-affected harmful factors
If passivation layers are extended to cover metallic structures in the edge termination region, then protection from electrical and chemical contaminants is improved, but crevice corrosion is promoted due to moisture trapping
Solution Approach 1:
The patent extracts the problematic combination of metal structures with overhanging passivation layers that create crevices. By removing metal from the edge termination region, the harmful crevice geometry is eliminated, allowing passivation layers to be applied without trapping moisture.
Solution Approach 2:
Instead of extending passivation layers over metal structures (which causes crevice corrosion), the patent inverts the approach by removing metal structures first, then applying passivation layers only to the semiconductor surface and insulation layers, eliminating the crevice formation mechanism.
3Object-affected harmful factors
If polysilicon field plates are used to reduce corrosion susceptibility, then protection from humidity and electric fields is improved, but metallic layers are still required for electric contact, maintaining corrosion risk
Solution Approach 1:
The patent merges the functions of field plates and metal contact structures into a single polysilicon-based system. The polysilicon field rings and field plates are directly connected to the semiconductor regions, eliminating the need for separate metallic interconnect layers in the edge termination region while maintaining electrical functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances the reliability and ruggedness of power semiconductor devices by shielding metallic structures from high electric fields and preventing crevice corrosion, thereby maintaining performance under high voltage and humidity conditions.
Implementation Method 1
a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 μm
Implementation Method 2
the protection region is configured to accommodate a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge
Data Source
AI summary
A power semiconductor device having a power semiconductor transistor configuration includes: a semiconductor body having a front side coupled to a first load terminal structure, a backside coupled to a second load terminal structure, and a lateral chip edge; an active region for conducting a load current in a conducting state; and an edge termination region separating the active region and lateral chip edge. At the front-side, the edge termination region includes a protection region devoid of any metallic structure, unless the metallic structure is electrically shielded from below by a polysilicon layer that extends further towards the lateral chip edge than the metallic structure by a lateral distance of at least 20 μm. In a blocking state, the protection region accommodates a voltage change of at least 90% of a blocking voltage inside the semiconductor body in a lateral direction from the active region towards the lateral chip edge.