Power Semiconductor Device With Field-Limiting Rings

Solution Overview

Problem

Current power semiconductor devices face challenges in achieving a balance between low ON-state voltage and high breaking capability, particularly during recovery operations, and there is a need to reduce manufacturing costs while maintaining performance, including the goal of reducing chip size without compromising functionality.

Innovation Solution

The power semiconductor device incorporates a semiconductor substrate with a drift region, well region, extension region, and field-limiting rings, along with a specific configuration of electrodes and insulating films to manage electric field strength and temperature distribution, allowing for a smaller chip size with enhanced breaking capability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the chip size is reduced, then manufacturing cost decreases and productivity increases, but breaking capability during turn-off operation deteriorates due to increased electric field strength and thermal breakdown risk

Engineering Contradiction:

Improvenumber of chips per waferVSAvoidbreaking capability during turn-off operation

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by introducing lattice defects selectively in the termination region while keeping the extraction region free of lattice defects. This creates different carrier annihilation characteristics in different regions: the termination region with lattice defects facilitates carrier annihilation to reduce carrier concentration and electric field strength, while the extraction region without lattice defects maintains low ON-state voltage. This localized differentiation resolves the contradiction by enabling small chip size with adequate breaking capability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent segments the device into distinct functional regions: an extraction region between the transistor region and termination region, and a termination region around the transistor region. By segmenting the chip structure and applying different lattice defect configurations to different segments, the patent achieves both low ON-state voltage in the extraction region and high breaking capability in the termination region, allowing reduced chip size without sacrificing reliability.

Inventive Principle:

Principle #1Segmentation

2Reliability

If lattice defects are introduced in the extraction region, then breaking capability improves through accelerated carrier annihilation, but ON-state voltage increases due to additional recombination centers

Engineering Contradiction:

Improvebreaking capabilityVSAvoidON-state voltage

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies local quality by introducing lattice defects selectively in the termination region while keeping the extraction region free of lattice defects. This creates different carrier annihilation characteristics in different regions: the termination region with lattice defects facilitates carrier annihilation to reduce carrier concentration and electric field strength, while the extraction region without lattice defects maintains low ON-state voltage. This localized differentiation resolves the contradiction by enabling small chip size with adequate breaking capability.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration effectively suppresses electric field strength and local temperature rises, enabling both a small chip size and high static and dynamic breaking capability, while maintaining low ON-state voltage and reducing manufacturing costs by increasing chip production from a single wafer.

Implementation Method 1

a plurality of field-limiting rings of the second conductivity type... each of the field-limiting rings together with the drift region located on the inner side forms a unit structure

Methodology Applied

Scientific EffectElectric field confinement: Electric Field

Implementation Method 2

This configuration effectively suppresses electric field strength and local temperature rises

Methodology Applied

Scientific EffectThermal conduction: Conduction (thermal)

Data Source

PatentUS9941269B2Power semiconductor device including well extension region and field-limiting rings

Publication Date: 2018.04.10 MITSUBISHI ELECTRIC CORP

AI summary

A drift region has a first conductivity type. A well region is at least partially included in an interface area, has an end portion between the interface area and an edge termination area, and has a second conductivity type. An extension region extends outward from the well region, is shallower than the well region, and has the second conductivity type. A plurality of field-limiting rings are provided outside the extension region in the edge termination area. Each of the field-limiting rings together with the drift region located on the inner side forms a unit structure. The field-limiting ring located closer to the outside has a lower proportion of a width to a width of the unit structure. The unit structure located closer to the outside has a lower average dose.