Power Semiconductor Device with Floating Field Rings
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Solution Overview
Problem
Existing power semiconductor devices face limitations in achieving high blocking voltage, low thermal resistance, low parasitic resistance, compact size, and high current performance, particularly in structures using high heat-conductivity insulating resins and sealing methods that do not effectively prevent blocking voltage deterioration.
Innovation Solution
The design incorporates an emitter region, a high resistance region, and a floating field ring structure, with conductive bonding materials and a multilayer substrate to separate the high blocking voltage ensuring region from the first electrode wiring, allowing for elevated blocking voltage and efficient heat radiation, while using a two-surface heat radiation structure for enhanced current performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If high heat-conductivity insulating resin is mounted on and under the module to reduce thermal resistance, then heat radiation is enhanced, but blocking voltage deteriorates
Solution Approach 1:
The patent divides the semiconductor device structure into distinct regions: a first semiconductor region (emitter) and a second semiconductor region (collector) separated by an insulating layer. This segmentation allows the insulating resin to be positioned specifically without directly contacting the high-voltage regions, thus maintaining blocking voltage while enabling thermal conduction paths through the insulating substrates.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the first and second semiconductor regions. This insulating layer acts as a mediator that prevents direct electrical contact (maintaining blocking voltage) while allowing thermal energy to pass through the high heat-conductivity insulating resin mounted on the insulating substrates.
2Reliability
If semiconductor chip is joined to multilayer substrate by wiring to achieve electrical connection, then electrical conduction is established, but thermal resistance increases and compact size is reduced
Solution Approach 1:
The patent extracts the thermal conduction function from the electrical wiring structure. Instead of relying on wiring to provide both electrical connection and thermal conduction, the invention separates these functions: wiring provides electrical connection while dedicated high heat-conductivity insulating substrates provide thermal conduction paths, reducing overall thermal resistance.
Solution Approach 2:
The multilayer substrate structure serves multiple functions simultaneously: it provides electrical connection through conductive layers, thermal conduction through high heat-conductivity insulating materials, and mechanical support. This multi-functionality reduces the need for separate components, achieving compact size while maintaining low thermal resistance.
3Volume of moving object
If semiconductor chip size is reduced to achieve compact device, then device size is reduced, but current performance deteriorates
Solution Approach 1:
The patent applies local quality by concentrating high heat-conductivity insulating materials specifically at the thermal conduction paths (under and around the semiconductor chip) rather than uniformly throughout the entire device. This allows efficient heat dissipation from the compact chip, maintaining current performance despite reduced size.
Solution Approach 2:
The patent uses composite material structures combining semiconductor chips with high heat-conductivity insulating substrates and insulating layers. This composite approach enables the compact chip to maintain high current performance by effectively managing heat dissipation through the composite thermal conduction paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves high blocking voltage, low thermal resistance, low parasitic resistance, compact size, and high current performance by effectively managing the depletion layer and electric field, preventing blocking voltage deterioration and enabling efficient heat dissipation.
Implementation Method 1
high heat-conductivity insulating resin, in stead of metal, was mounted on and under the module, there was limitation in reduction of thermal resistance
Implementation Method 2
when voltage is applied to the first electrode and the second electrode, a depletion layer in the lateral direction spreads between p-type regions 26 and 30, and n-type regions 27 and 29
Implementation Method 3
the first electrode wiring layers 16a and 16c, and the emitter electrode pad 23 and the anode electrode pad 33, which are the first electrode pads, by conductive bonding materials 18a and 18c
Data Source
AI summary
A power semiconductor device, having a first semiconductor region, and a second semiconductor region; mounted with a first electrode pad on a semiconductor substrate main surface at the inside surrounded by the third semiconductor region, mounted in the second semiconductor region, and a multilayer substrate having first and second wiring layers, to take out an electrode of the semiconductor chip; joining the first wiring layer part for the first electrode, mounted on the multilayer substrate, in a region opposing to the semiconductor substrate main surface at the inside surrounded by the third semiconductor region, and the first electrode pad, by a conductive material; joining the first wiring layer part for the first electrode, and the second wiring layer at a conductive part; and extending the second wiring layer to the outside of a region opposing the semiconductor substrate main surface at the inside surrounded by the third semiconductor region.