Power Semiconductor Device Floating Region for BVCES and Vce(sat)
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Solution Overview
Problem
Existing power semiconductor devices face challenges in minimizing Collector-Emitter Saturation Voltage (Vce(sat)) and maintaining high switching performance while securing Breakdown Voltage Collector-Emitter (BVCES), as alternative technologies either increase Vce(sat) or reduce switching performance by modifying the Epi layer thickness.
Innovation Solution
A method of manufacturing power semiconductor devices involves forming trenches in a substrate with a P-type base region, performing specific implantation processes to create P+ and N+ doped regions, and forming a floating region deeper than usual to encompass the underside of the trench structure, reducing the concentrated electric field and enhancing switching performance without compromising BVCES.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the floating interval of the IEGT is minimized or the resistivity value of the Epi layer is increased to secure BVCES, then the breakdown voltage between collector and emitter is improved, but the Collector-Emitter Saturation Voltage increases and switching performance deteriorates
Solution Approach 1:
The patent applies local quality by creating a floating region with specific P-type doping characteristics at a localized depth range (0.5-2.0 μm from the first surface) within the N-type drift layer. This localized doped region provides electric field modulation exactly where needed to enhance breakdown voltage, while the rest of the device structure maintains optimal characteristics for low saturation voltage and high switching performance.
Solution Approach 2:
The patent utilizes parameter changes by precisely controlling the doping concentration (1×10^16 to 1×10^18 atoms/cm³) and depth position of the floating region. By adjusting these parameters, the electric field distribution is optimized to achieve higher breakdown voltage without the trade-off of increased saturation voltage, as the floating region subtly modulates the field without creating excessive resistance.
2Reliability
If the thickness of the Epi layer is increased to secure BVCES, then the breakdown voltage is improved, but the switching performance is reduced
Solution Approach 1:
Instead of uniformly increasing the entire Epi layer thickness, the patent introduces a localized floating region with P-type doping at a specific depth within the N-type drift layer. This localized modification provides the necessary breakdown voltage enhancement without increasing the overall layer thickness that would degrade switching performance.
Solution Approach 2:
The patent segments the Epi layer into functionally distinct regions: the N-type drift layer for current conduction, and the embedded P-type floating region for electric field control. This segmentation allows each region to be optimized independently - the N-type layer maintains thinness for fast switching, while the P-type floating region provides breakdown voltage enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces gate capacitance and energy consumption while maintaining BVCES, resulting in improved switching performance and lower power consumption.
Implementation Method 1
performing a first implantation process using P-type dopants implanted onto the P-type base region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region
Data Source
AI summary
A method of manufacturing a power semiconductor device includes forming trenches in a substrate, wherein the substrate includes a first surface and a second surface opposite to the first surface, forming a gate insulating layer and a gate electrode in each of the trenches, forming a P-type base region between the trenches in the substrate, performing a first implantation process using P-type dopants implanted onto the P-type base region, forming an N+ source region in the substrate, forming an interlayer insulating layer on the N+ source region, performing a second implantation process using P-type dopants to form a P+ doped region on the P-type base region, forming an emitter electrode in contact with the N+ source region and the P+ doped region, forming a P-type collector region on the second surface of the substrate, and forming a drain electrode on the P-type collector region.