Power Semiconductor Gate Control Circuit for Overheat Protection

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Solution Overview

Problem

Existing power semiconductor devices in ignition systems for internal combustion engines lack effective protection mechanisms to prevent malfunctions due to overheating, leading to potential damage and malfunction of the ignition apparatus and connected components.

Innovation Solution

A semiconductor apparatus with a cutoff condition detection portion, a reset portion, a latch portion, and a prevention circuit that controls the power semiconductor element to switch to an OFF state upon detecting abnormal conditions, preventing the gate from being at an ON potential during reset periods, even if the cutoff condition is met, thereby preventing overheating and malfunctions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the power semiconductor device operates continuously without protection mechanisms, then productivity is maintained, but reliability deteriorates due to overheating and malfunctions

Engineering Contradiction:
Improveprotection against overheatingVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements preliminary protection actions by detecting abnormal conditions (overheat, overcurrent, overvoltage) before they cause damage. The cutoff condition detection portion continuously monitors parameters and triggers protective cutoff before overheating or malfunctions occur, preventing harm rather than reacting to it.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces intermediary protective circuits between the power semiconductor device and the abnormal conditions. The cutoff condition detection portion, latch portion, and cutoff circuit act as intermediaries that detect, process, and respond to abnormal conditions, isolating the power device from direct exposure to harmful effects.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Ease of operation

If the gate is allowed to be at ON potential during reset period, then ease of operation is improved, but harmful factors increase due to potential overheating

Engineering Contradiction:
Improvereset operationVSAvoidoverheating risk
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by using the prevention circuit to block the gate signal during the reset period. Even if the control signal attempts to turn the gate ON, the prevention circuit prevents this action during the vulnerable reset period when the power device is susceptible to overheating, counteracting potential harmful effects before they can occur.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent provides beforehand cushioning by extending the protective effect beyond the basic reset period. The prevention circuit maintains the gate in OFF state not only during reset but also for a predetermined period afterward, cushioning against potential abnormal conditions that might arise during or after the reset operation.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS9899804B2Semiconductor apparatus
Publication Date: 2018.02.20 FUJI ELECTRIC CO LTD
  • US9899804B2 patent drawing
  • US9899804B2 patent drawing
  • US9899804B2 patent drawing

AI summary

A semiconductor apparatus is provided, including a power semiconductor element, a cutoff condition detection portion which detects whether a predetermined cutoff condition is met, a reset portion which outputs a reset signal that instructs to reset during a predetermined period in response to an input of the control signal turning the power semiconductor element on, a latch portion which is reset in response to the reset signal and latches that an occurrence of the cutoff condition is detected after the reset, a cutoff circuit which controls the gate of the power semiconductor element to be at an OFF potential in response to the latching of the occurrence of the cutoff condition by the latch portion, and a prevention circuit which prevents the gate of the power semiconductor element from being at an ON potential during a period of reset of the latch portion even if the cutoff condition is met.