Power Semiconductor Layout for Lower JFET and Contact Resistance
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Solution Overview
Problem
Current power semiconductor devices face limitations in reducing parasitic junction-FET (JFET) effects and contact resistance, which hinder increased current densities and lead to higher parasitic gate/drain capacitance with down-scaling, especially in trench designs.
Innovation Solution
The proposed solution involves a vertical power semiconductor device design with a raised source and drift region, where the gate electrode is laterally positioned next to the main electrode, and the contact region projects beyond the base region, allowing for reduced contact resistance and elimination of parasitic gate/drain capacitance, enabling enhanced switching performance and chip size reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional separate production processes are used for insulating films and semiconductor elements, then manufacturing flexibility is maintained, but production time increases and productivity decreases
Solution Approach 1:
The patent combines the production of insulating films and semiconductor elements into a single integrated substrate. The insulating film layer and semiconductor element layer are formed on the same substrate simultaneously, eliminating the need for separate production processes and subsequent bonding operations. This merging of previously separate processes directly reduces production time and increases productivity while maintaining manufacturing flexibility through the layered structure design.
2Manufacturing precision
If multiple separate production processes are used for different components, then manufacturing precision can be maintained for each component, but the overall alignment precision deteriorates due to bonding processes
Solution Approach 1:
By forming insulating films and semiconductor elements on a single substrate simultaneously, the patent eliminates bonding processes that cause alignment errors. The integrated production approach ensures that all components are precisely positioned relative to each other from the outset, maintaining high manufacturing precision while improving production efficiency through process integration.
3Productivity
If conventional bonding processes are used to connect insulating films and semiconductor elements, then device functionality is achieved, but production time increases and productivity decreases
Solution Approach 1:
The patent integrates the formation of insulating films and semiconductor elements into a single production process on one substrate, eliminating the need for separate bonding operations. This approach maintains device functionality by ensuring proper electrical and structural connections are established during the integrated fabrication process, while simultaneously reducing production time and improving productivity.
4Ease of manufacture
If separate production processes are used for insulating films and semiconductor elements, then ease of manufacture is maintained, but manufacturing cost increases due to multiple processes
Solution Approach 1:
The patent combines the production of insulating films and semiconductor elements on a single substrate, allowing for more efficient material usage. By integrating the processes, the patent reduces material waste associated with separate production and bonding operations, while maintaining ease of manufacture through standardized fabrication techniques applied to the integrated structure.
Data Source
AI summary
Power semiconductor device and method for producing a power semiconductor device The power semiconductor device (100) comprises a semiconductor body (1) with a top side (10), a main electrode (2) on the top side and a gate electrode (3) on the top side and arranged next to the main electrode in a first lateral direction (L1). The semiconductor body comprises a drift layer (11) of a first conductivity type, a base region (12) of a second conductivity type arranged vertically between the drift layer and the top side, a contact region (13) of the first conductivity type arranged vertically between the drift layer and the top side. The contact region adjoins the base region and the top side. Furthermore, the semiconductor body comprises a drift region (14) of the first conductivity type arranged next to the base region in the first lateral direction and adjoining the base region. The main electrode is in electrical contact with the contact region. In plan view of the top side, the gate electrode at least partially covers a channel portion (12a) of the base region which lies, in the first lateral direction, between the contact region and the drift region. At the top side, at least one of the contact region and the drift region projects beyond the base region in vertical direction.