Power Semiconductor Device Leakage Reduction
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Solution Overview
Problem
High-voltage integrated circuits with integrated bootstrap diodes suffer from significant leakage current, leading to increased module size and manufacturing costs when separate chips or charge pump blocks are used to mitigate this issue.
Innovation Solution
A power semiconductor device design incorporating a substrate with strategically positioned n-type buried layers and impurity regions to reduce leakage current, including a p-n junction diode structure and element isolation regions, allowing for monolithic integration of high-voltage and low-voltage circuits without the need for additional charge pump circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a bootstrap diode is integrated on a high-voltage integrated circuit in a monolithic fashion, then device complexity is reduced, but leakage current increases significantly
Solution Approach 1:
The patent applies local quality by creating an n-type buried layer with high impurity concentration specifically at the bottom of the substrate where the bootstrap diode is formed. This localized modification of impurity concentration in the n-type region prevents hole accumulation and reduces leakage current from the anode to substrate, while maintaining the benefits of monolithic integration.
2Object-generated harmful factors
If two chips are disposed inside one package or a synchronous rectifier with a separate charge pump block is used, then leakage current is reduced, but module size and manufacturing costs increase
Solution Approach 1:
The patent merges the bootstrap diode functionality directly into the high-voltage integrated circuit chip using monolithic integration. By combining what would traditionally require separate chips or charge pump blocks into a single integrated structure with the n-type buried layer, the invention reduces module size while maintaining low leakage current performance.
Solution Approach 2:
The n-type buried layer structure enables the integrated circuit to self-manage leakage current suppression without requiring external charge pump circuits or separate compensation components. The high impurity concentration n-type region inherently prevents hole accumulation and leakage, making the device self-sufficient.
3Ease of manufacture
If a bootstrap diode is integrated monolithically, then manufacturing costs are reduced, but leakage current increases
Solution Approach 1:
The patent changes the impurity concentration parameter by creating an n-type buried layer with high impurity concentration (greater than 1×10^19 atoms/cm³) at the substrate bottom. This parameter modification enables the monolithic integrated bootstrap diode to achieve low leakage current while maintaining manufacturing cost advantages through single-chip integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a significant reduction in substrate leakage current while maintaining high breakdown voltage, enabling compact and cost-effective power semiconductor device modules with integrated high-voltage and low-voltage circuits.
Implementation Method 1
an n-type buried layer disposed below the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration inside the substrate
Data Source
AI summary
A power semiconductor device includes a substrate including a first epitaxial layer, a second epitaxial layer, and a base substrate where the first epitaxial layer is disposed between the second epitaxial layer and the base substrate. The power semiconductor device includes an anode electrode and a cathode electrode disposed on the substrate, a well region disposed inside the substrate in a lower portion of the anode electrode, and having p-type conductivity. The power semiconductor device includes an NISO region disposed in a lower portion of the well region inside the substrate, and having a first n-type impurity concentration. The power semiconductor device includes an n-type buried layer disposed in a lower portion of the NISO region, and having a second impurity concentration greater than the first n-type impurity concentration, inside the substrate.