Power Semiconductor Module Hard Potting and Copper Metallization
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Solution Overview
Problem
Power semiconductor modules face insulation strength impairment due to detachment of soft potting compounds from components at high temperatures, leading to cavity and crack formation.
Innovation Solution
A power semiconductor module design featuring a copper or copper alloy upper chip metallization with a thickness of at least 1 μm and copper-based connection conductors, combined with a potting compound having a penetration of less than or equal to 30 according to DIN ISO 2137, which completely covers the power semiconductor chip and connection conductors, enhancing mechanical stability and preventing cavity formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a soft potting compound is used to fill the power semiconductor module, then the module can be manufactured with conventional materials, but the potting compound becomes detached from components at high temperatures causing cavity and crack formation
Solution Approach 1:
The patent changes the key parameter of the potting compound from soft (conventional) to hard, specifically specifying a penetration depth of 2-5 mm according to DIN ISO 2137. This parameter change enables the potting compound to maintain its mechanical properties and adhesion at high temperatures, preventing detachment and cavity formation while still allowing conventional manufacturing processes to be used.
Solution Approach 2:
The patent employs a composite material system consisting of a hard potting compound combined with a copper or copper alloy metallization layer (minimum 1 μm thick) on the power semiconductor chip. This composite structure provides both mechanical stability and thermal conductivity, enabling the potting compound to withstand high temperature operations without detaching from the chip while maintaining ease of manufacture.
2Power
If the permissible junction temperature is increased to improve power semiconductor chip performance, then higher power output is achieved, but cavity and crack formation increases due to thermal stress
Solution Approach 1:
The patent changes the thermal management parameter by specifying a copper or copper alloy metallization layer with minimum 1 μm thickness on the power semiconductor chip. This parameter change enhances thermal conductivity at the chip level, enabling effective heat dissipation at higher junction temperatures and reducing thermal stress that would otherwise cause cavity and crack formation.
Solution Approach 2:
The patent uses a composite material system combining hard potting compound with copper-based metallization to create a thermally conductive and mechanically stable structure. This composite enables the module to operate at elevated junction temperatures while maintaining structural integrity by distributing and dissipating thermal stress uniformly throughout the assembly.
3Reliability
If a hard potting compound is used to prevent detachment at high temperatures, then insulation strength is maintained, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a precise parameter range for the hard potting compound penetration depth (2-5 mm according to DIN ISO 2137) to balance the contradiction. This parameter definition provides clear manufacturing targets that maintain insulation strength and prevent detachment while being achievable with conventional manufacturing tolerances, thus resolving the precision requirement issue.
Data Source
AI summary
A power semiconductor module includes a circuit carrier including an insulation carrier having a top side on which a metallization layer is arranged. A power semiconductor chip is arranged on a side of the metallization layer facing away from the insulation carrier, and which has on a top side of the power semiconductor chip facing away from the circuit carrier an upper chip metallization composed of copper or a copper alloy having a thickness of greater than or equal to 1 μm. An electrical connection conductor composed of copper or a copper alloy is connected to the upper chip metallization at a connecting location. A potting compound extends from the circuit carrier to at least over the top side of the power semiconductor chip and completely covers the top side of the power semiconductor chip, encloses the connection conductor at least in the region of the connecting location, and has a penetration of less than or equal to 30 according to DIN ISO 2137 at a temperature of 25° C.