Power Semiconductor Module With Integrated Drive Electronics

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current power semiconductor modules require complex constructions with many individual components and method steps due to the separate implementation of power semiconductor components and drive circuits on independent circuit boards, leading to elaborate and inefficient electrical connections.

Innovation Solution

A power semiconductor module with a ceramic substrate featuring patterned metallization of fine detail, where semiconductor chips and a ceramic capacitor are integrated, allowing for thin-wire bonding and reduced surface roughness to improve bondability and simplify the integration of drive electronics directly on the substrate, reducing the need for multiple components and connections.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If drive electronics are implemented on a separate circuit board, then electrical connection between power semiconductor components and drive electronics is achieved, but construction complexity increases and bondability deteriorates

Engineering Contradiction:
Improveelectrical connection reliabilityVSAvoidconstruction complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the drive electronics and power semiconductor components onto a single ceramic substrate, eliminating the separate circuit board arrangement. This integration reduces construction complexity by consolidating multiple components and connection steps into a unified structure, while maintaining reliable electrical connections through direct bonding on the substrate.

Inventive Principle:
Principle #5Merging (Combining)

2Ease of manufacture

If traditional circuit board implementation is used, then drive electronics can be mounted independently, but bondability and connection efficiency deteriorate

Engineering Contradiction:
Improveindependent mounting capabilityVSAvoidbondability
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The patent applies local quality by creating specifically optimized bonding regions on the ceramic substrate with appropriate metallization patterns and surface characteristics. These localized areas provide enhanced bondability for the thin-wire bonds connecting drive electronics to power semiconductor components, while the rest of the substrate maintains its structural and electrical functions.

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If thin-wire bonding with diameter ≤75 μm is used, then connection precision and integration density improve, but manufacturing difficulty increases

Engineering Contradiction:
Improveconnection precisionVSAvoidmanufacturing difficulty
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by pre-preparing the ceramic substrate with optimized metallization layers and surface treatments before bonding the thin-wire connections. The substrate is pre-configured with appropriate bonding pads, metallization patterns, and surface roughness characteristics that facilitate successful thin-wire bonding, thereby reducing the actual bonding difficulty despite using fine-pitch wires with diameter ≤75 μm.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS7579682B2Power semiconductor module
Publication Date: 2009.08.25 INFINEON TECHNOLOGIES AG
  • US7579682B2 patent drawing
  • US7579682B2 patent drawing
  • US7579682B2 patent drawing

AI summary

A power semiconductor module has a ceramic substrate (9) which has on at least one side a patterned metallization (50) with a fineness of pattern of smaller than or equal to 800 μm, a first semiconductor chip (10) which has a power semiconductor component and which is arranged on the patterned metallization (50), and a second semiconductor chip (30) which has drive electronics for driving the first semiconductor chip (10) and which is arranged on the patterned metallization (50). Furthermore, at least one thin-wire bond (2, 3) with a bonding-wire diameter (d2, d3) of smaller than or equal to 75 μm is provided which is formed between the patterned metallization (50) and the second semiconductor chip (30).