Power Semiconductor Module Leadframe Configuration for Stray Inductance Reduction
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Solution Overview
Problem
Conventional inverter power modules face limitations in power and temperature ratings, switching symmetry, and compactness due to the need for high-cost solderable frontside metallizations and bond technologies that require chip distribution in two dimensions, leading to increased yield loss and thermal stress issues.
Innovation Solution
A power semiconductor module design featuring a leadframe with die pads and power leads arranged in a configuration that allows parallel electrical connections in a single direction, reducing bond length and temperature, and enabling scalable and cost-effective production by eliminating the need for 90° rotation of low-side switch devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If chips are distributed in two different dimensions to provide sufficient wire cross section for current carrying, then the current carrying capability is improved, but the module compactness deteriorates
Solution Approach 1:
The patent transitions from two-dimensional chip distribution to a three-dimensional stacked configuration. Multiple chip stacks are vertically arranged above the substrate, allowing sufficient wire cross-section for current carrying while maintaining compact horizontal footprint. The vertical stacking enables more chips to be accommodated in a smaller planar area.
Solution Approach 2:
The patent implements nested arrangement where multiple chip stacks are vertically positioned one above another. The lower chips are nested beneath upper chips in the vertical dimension, maximizing space utilization and achieving compact module design while providing adequate current path cross-section through the stacked configuration.
2Productivity
If one large chip is used to implement both high-side and low-side switch devices, then chip count is reduced, but solder void rate increases leading to yield loss
Solution Approach 1:
The patent divides the power switch implementation into separate high-side and low-side chip stacks rather than using one large integrated chip. Each stack contains chips of appropriate size that can be reliably soldered to the substrate, avoiding the solder void issues associated with large single chips while achieving the desired functionality through multiple smaller, more reliable connections.
3Ease of manufacture
If low-side dies are rotated by 90° relative to high-side dies to use the same amount of wire bonds, then wire bond utilization is improved, but power scalability is limited
Solution Approach 1:
The patent creates a universal chip stack configuration where all chips are oriented in the same direction and arranged in stacks. This standardized orientation makes the module universally scalable - additional chip stacks can be added vertically without requiring rotational adjustments or special wiring arrangements, enabling easy power scaling while maintaining consistent wire bond patterns.
4Ease of operation
If conventional leadframe concepts are used with separate die pads for high-side and low-side switches, then routing capability is maintained, but phase connection complexity increases
Solution Approach 1:
The patent merges the phase connection function into the substrate structure itself. The substrate provides direct electrical connection between corresponding chips in high-side and low-side stacks, eliminating the need for separate phase connection elements like copper clips. This integration simplifies the overall phase connection architecture while maintaining routing capability through the substrate's conductive paths.
Data Source
AI summary
A power semiconductor module includes a leadframe having a first die pad, a second die pad separated from the first die pad, a first power lead formed as an extension of the first die pad, a second power lead separated from the first and second die pads, and a first connection region formed as an extension of the second power lead alongside the second die pad. A first plurality of power semiconductor dies is attached to the first die pad and electrically coupled in parallel. A second plurality of power semiconductor dies is attached to the second die pad and electrically coupled in parallel. A first electrical connection extends between the first plurality of power semiconductor dies and the second die pad in a first direction. A second electrical connection extends between the second plurality of power semiconductor dies and the first connection region in the first direction.