Power Semiconductor Package With Nanowire Interconnects for Thermal Stress
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Solution Overview
Problem
Power semiconductors face failure due to thermo-mechanical stress from coefficient of thermal expansion mismatches and thermal gradients, which damages interconnections made by wire bonding and laser-drilled micro vias are not flexible enough to absorb mechanical displacements effectively.
Innovation Solution
The method involves growing high aspect ratio nanowires on power semiconductor electrodes using electro-deposition within templates, which are then embedded in a prepeg panel, allowing for flexibility and protection during handling, and forming a conductive structure that can endure mechanical deformation while conducting current and heat.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonds are used to electrically connect power semiconductor to external components, then electrical connection is achieved, but the interconnection is damaged under thermo-mechanical stress leading to failure
Solution Approach 1:
The patent uses a thin foil with aperture instead of rigid wire bonds or micro vias. The foil structure is flexible and can deform under thermal expansion and mechanical stress without breaking, while the aperture provides electrical connection. This resolves the contradiction by providing both reliability and stress resistance through the flexible foil design.
Solution Approach 2:
The patent employs a foil with aperture (porous structure) that allows electrical connection while accommodating thermal expansion. The porous/aperforated design enables the interconnection to absorb mechanical displacements through deformation, maintaining reliability under thermo-mechanical stress.
2Reliability
If laser drilled micro vias are used to connect power semiconductor to PCB, then parasitic inductance is improved, but flexibility under thermal and mechanical stress is not optimal
Solution Approach 1:
The patent replaces rigid laser-drilled micro vias with a flexible thin foil containing an aperture. The foil can bend and deform under thermal and mechanical stress, providing the needed flexibility while maintaining electrical connection quality, thus resolving the contradiction between connection quality and stress flexibility.
Solution Approach 2:
The patent introduces a dynamic, flexible foil structure that can adapt its shape under stress, unlike the static rigid micro vias. The foil's ability to deform dynamically allows it to maintain electrical connection while accommodating thermal expansion and mechanical displacements.
3Adaptability or versatility
If nano wires with high aspect ratio are used to provide flexibility, then deformation under mechanical stress is absorbed, but manufacturing complexity increases
Solution Approach 1:
The patent extracts the essential function of flexibility from complex nanowire forests and implements it through a simpler thin foil with aperture. The foil provides the necessary deformation capability without requiring complex nanowire structures, thus reducing manufacturing complexity while maintaining flexibility.
Solution Approach 2:
The patent uses a simple, inexpensive thin foil instead of complex, expensive nanowire forests. The foil is a straightforward, easy-to-manufacture component that provides the needed flexibility without the manufacturing complexity of nanowire structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The nanowire structure enhances the robustness of power semiconductor assemblies against mechanical stress, maintaining electrical and thermal conductivity, and controlling junction temperature by absorbing thermal displacements without damaging the connections.
Implementation Method 1
electro-depositing of a conducting material for nanowire formation over the electrodes of the power semiconductor, the nanowire formation being performed within the templates
Implementation Method 2
curing the prepeg panel
Data Source
Figure 1
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AI summary
The present invention concerns a method for manufacturing a package of a power semiconductor and a package comprising a power semiconductor (200). The package comprises: - conducting layers (240a,240b, 240c) over each electrode (250a,250b,250c) of the power semiconductor, - nanowires (500a, 500b, 500c) over the part of the conducting layer that are over the electrodes, - cured prepeg (700a, 700b) on each side of the power semiconductor and over (910b) a part of a masking film that separate two electrodes, - conducting layers (110a, 110b)) over nanowires, the conducting layers over each electrode of the power semiconductor, the nanowires and the conducting layers over the nanowires forming a single conductor unit.