Multi-Chip Power Semiconductor Package Creepage Structure

The patent introduces a three-dimensional stacked arrangement of multiple power semiconductor chips (first chip, second chip, third chip) vertically positioned on the semiconductor substrate. This vertical stacking in the third dimension increases the effective power handling capability without proportionally increasing the planar footprint, while distributing heat generation across multiple separated chips rather than concentrating it in a single device.

The patent divides the power semiconductor functionality into multiple separate chips (first power semiconductor chip, second power semiconductor chip, third power semiconductor chip) that are stacked vertically. Each chip handles a portion of the power conversion task, segmenting the overall power handling function. This segmentation distributes the heat generation across multiple discrete sources, making thermal management more effective compared to a single high-power chip.

The patent introduces intermediate spacer layers (first spacer layer, second spacer layer) positioned between the stacked power semiconductor chips. These spacers serve as thermal intermediaries that conduct heat away from each chip to dedicated heat dissipation regions on the substrate, preventing heat accumulation between the closely spaced chips while maintaining electrical isolation and mechanical support.

The patent employs multiple identical or similar power semiconductor chips (first chip, second chip, third chip) stacked in sequence, each with its own heat dissipation path through the substrate. This copying approach allows each chip to be treated as an independent thermal source with its own heat sink, simplifying thermal management compared to trying to dissipate heat from a single high-power device or complex thermal interface between chips.

The patent utilizes the vertical dimension by stacking power semiconductor chips and creepage structures in the third dimension rather than requiring increased lateral separation. The anti-series connection configuration and vertical stacking allow creepage paths to extend vertically through the stack, achieving required creepage distances without proportionally increasing the planar package footprint.

The patent implements creepage structures specifically at critical locations where high voltage potentials exist (between anti-series connected chips and to the substrate), rather than uniformly increasing distances everywhere. The spacer layers and substrate regions provide localized creepage enhancement precisely where pollution degree requirements are most stringent, maintaining compact overall dimensions.