Power Semiconductor Device Planar Metal Interface
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Solution Overview
Problem
Conventional power semiconductor devices experience early breakdown due to point discharges between source metal patterns and drain metal patterns, limiting the thickness and width of these patterns for large current transmission.
Innovation Solution
The design includes a substrate with a gate electrode and electrodes on either side, where the source and drain metal patterns are positioned at different sides with a planar interface to the underlying insulating layer, allowing for wider dimensions without sharp corners to prevent point discharges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the source metal pattern and drain metal pattern are made wider and thicker for large current transmission, then current transmission capability is improved, but point discharge occurs between the patterns causing early breakdown
Solution Approach 1:
The patent introduces a planarization layer between the source/drain metal patterns and the underlying insulating layer, creating an additional dimensional level. This planarization surface eliminates sharp corners and protrusions at the metal-insulating layer interface, preventing point discharge while allowing the metal patterns to maintain larger cross-sectional areas for improved current transmission capability.
2Loss of energy
If the metal patterns have larger cross-sectional area for lower resistance, then power efficiency is improved, but the interface with insulating layer creates sharp corners leading to point discharge
Solution Approach 1:
The patent applies planarization processing to create a flat, curved-free surface at the interface between the metal patterns and the insulating layer. By eliminating sharp corners and protrusions through this planarization step, the design prevents point discharge phenomena while maintaining the large cross-sectional area of metal patterns needed for low resistance and high power efficiency.
Data Source
AI summary
A power semiconductor device and a method for fabricating the same are provided. The power semiconductor device includes a substrate and an active layer on the substrate. A gate electrode is disposed on the active layer. A first electrode and a second electrode are disposed on the active layer, on opposite sides of the gate electrode. A first metal pattern is coupled to the first electrode. A second metal pattern is coupled to the second electrode. A first insulating layer is disposed on the first and second metal patterns. A third metal pattern covers the first insulating layer, coupled to the second metal pattern. An interface between the third metal pattern and the first insulating layer is a substantially planar surface.