Power Semiconductor Device With Segmented Base Layer
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Solution Overview
Problem
Reverse-conducting power semiconductor devices face high on-state losses and voltage snap-back issues due to the p-base layer being shorted to the n-source region, limiting gate control during diode mode and affecting IGBT performance.
Innovation Solution
Incorporating a well of a second conductivity type outside the active IGBT cell, decoupled from the MOS channel, to reduce the influence of the MOS channel during forward conduction and introduce an additional diode emitter area, thereby optimizing diode performance independently from IGBT mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the p-base layer is shorted to the n-source region to form the diode structure, then the diode function is achieved, but the MOS channel shorts the p-n junction and prevents hole injection, causing voltage snap-back and high on-state losses
Solution Approach 1:
The base layer is segmented into two distinct regions: a first base layer region that forms the diode anode and is in direct contact with the emitter electrode, and a second base layer region that forms the IGBT base and is contacted by the gate electrode. This segmentation allows the diode and IGBT functions to operate independently without mutual interference, eliminating the voltage snap-back effect while maintaining low on-state losses.
Solution Approach 2:
The gate control function is extracted from the diode operation by providing a separate gate electrode that contacts only the second base layer region. This allows the MOS channel to be controlled independently from the diode current path, enabling the diode to operate without the harmful shorting effect of the MOS channel while the IGBT can still be controlled by the gate.
2Ease of operation
If the gate voltage is applied to control the IGBT, then the IGBT function is achieved, but the MOS channel extracts plasma from below the p-base layer and increases on-state losses
Solution Approach 1:
The base layer is divided into a first base layer region for diode operation and a second base layer region for IGBT operation. The gate electrode contacts only the second base layer region, allowing gate control to be applied selectively to the IGBT without affecting the diode region. This segmentation prevents the MOS channel from extracting plasma in the diode region, thereby reducing on-state losses.
Solution Approach 2:
The insulating layer acts as an intermediary between the gate electrode and the first base layer region. This insulating layer prevents the gate electrode from directly influencing the diode region while still allowing the gate to control the second base layer region for IGBT operation, thus isolating the gate control effect from the diode plasma.
3Device complexity
If the p-base layer is used for both diode anode and IGBT base, then device integration is achieved, but the MOS channel influence cannot be decoupled, limiting independent optimization
Solution Approach 1:
The base layer is segmented into a first base layer region and a second base layer region with different functions. The first base layer region serves as the diode anode and is contacted by the emitter electrode, while the second base layer region serves as the IGBT base and is contacted by the gate electrode. This segmentation enables independent optimization of diode and IGBT parameters without compromising device integration.
Solution Approach 2:
Different regions of the base layer are given different electrical properties and connections: the first base layer region is optimized for diode operation with direct emitter contact, while the second base layer region is optimized for IGBT operation with gate control. This local differentiation allows each region to be independently optimized for its specific function while maintaining overall device integration.
Data Source
AI summary
An exemplary power semiconductor device with a wafer having an emitter electrode on an emitter side and a collector electrode on a collector side, an (n-) doped drift layer, an n-doped first region, a p-doped base layer, an n-doped source region, and a gate electrode, all of which being formed between the emitter and collector electrodes. The emitter electrode contacts the base layer and the source region within a contact area. An active semiconductor cell is formed within the wafer, and includes layers that lie in orthogonal projection with respect to the emitter side of the contact area of the emitter electrode. The device also includes a p-doped well, which is arranged in the same plane as the base layer, but outside the active cell. The well is electrically connected to the emitter electrode at least one of directly or via the base layer.