Power Semiconductor Device With Segmented P-Well
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In power semiconductor devices, the large parasitic resistance and voltage drop in the P-well region lead to a high electric field across the gate insulating film during switching, potentially causing dielectric breakdown, especially when using silicon carbide as a substrate material which increases the challenge of reducing resistance and preventing breakdown at higher switching speeds.
Innovation Solution
The design includes a first and second conductivity-type well region with a smaller area second well region and a thicker field oxide film, where the gate electrode is positioned within the field oxide film and connected to the source electrode, reducing the electric field on the gate insulating film by minimizing the potential difference across the P-well and preventing dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the P-well area is increased to reduce parasitic resistance, then the voltage drop in the P-well is reduced, but the electric field across the gate insulating film increases during switching, leading to dielectric breakdown
Solution Approach 1:
The P-well region is segmented into two distinct parts: a first P-well region with larger area located apart from the contact hole, and a second P-well region with smaller area located near the contact hole. This segmentation allows each region to serve different functions - the first region provides low parasitic resistance while the second region maintains low electric field, thereby resolving the contradiction between reducing voltage drop and preventing dielectric breakdown.
Solution Approach 2:
Different regions of the P-well are given different properties through selective area design. The first P-well region has a larger area to reduce parasitic resistance and voltage drop, while the second P-well region has a smaller area to minimize the electric field across the gate insulating film. This local differentiation allows the system to simultaneously achieve low resistance and low electric field in different locations.
2Productivity
If the switching speed is increased to improve performance, then the power consumption is reduced, but the displacement current increases, causing larger voltage drops and higher electric fields that lead to dielectric breakdown
Solution Approach 1:
The segmented P-well structure enables different regions to handle different aspects of the displacement current problem. The first P-well region with larger area provides a lower impedance path for displacement current, reducing voltage drops during high-speed switching. The second P-well region with smaller area ensures that the electric field remains controlled, preventing dielectric breakdown even when displacement current increases due to higher switching speeds.
Solution Approach 2:
The invention changes the geometric parameters of the P-well regions to optimize performance. By adjusting the area of the first and second P-well regions, the parasitic resistance and electric field distribution are optimized to accommodate high-speed switching operations with large displacement currents without causing dielectric breakdown.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration prevents dielectric breakdown and enables higher-speed switching operations by reducing the electric field on the gate insulating film, even at high switching speeds, thus improving the reliability and performance of power semiconductor devices.
Implementation Method 1
the displacement current flowing into the P-well below the gate pad flows through the P-well below the gate pad from the cell direction of the MOSFET toward the contact hole connected to the field plate, and then flows into the source electrode through the field plate
Implementation Method 2
the drain voltage of the MOSFET cell, that is, the voltage of the drain electrode rises sharply, which changes from approximately 0 V to several hundreds V. As a result, a displacement current flows into the P-well through the parasitic capacitance occurring across the P-well and the N−-drain layer
Data Source
AI summary
A structure of a power semiconductor device, in which a P-well region having a large area and a gate electrode are opposed to each other through a field oxide film having a larger thickness than that of a gate insulating film such that the P-well region having a large area and the gate electrode are not opposed to each other through the gate insulating film, or the gate electrode is not provided above the gate insulating film that includes the P-well region having a large area therebelow.