Power Semiconductor Shrinkage Cavity Suppression via Wire Bonding

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Solution Overview

Problem

Shrinkage cavities in power semiconductor devices due to differing solidification points of bonding material elements lead to cracking and impaired heat radiation and wire bonding, with existing dimple processing methods compromising insulation and layout design freedom.

Innovation Solution

A power semiconductor device design featuring a heat radiation plate, insulating substrate, and semiconductor element bonded with a solder containing elements of different solidification points, where a metal wire is bonded around the semiconductor element to counteract shrinkage forces, preventing cavity formation and ensuring proper wire bonding without dimples on the substrate.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If dimple processing is applied to the back surface Cu pattern of an insulating substrate to suppress shrinkage cavity, then shrinkage cavity is suppressed, but vacancies are formed which compromise insulation and heat radiation performance

Engineering Contradiction:
Improveshrinkage cavity suppressionVSAvoidvacancy formation affecting insulation and heat radiation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The invention extracts the shrinkage cavity suppression function from the insulating substrate and relocates it to the heat radiation plate. By forming dimples on the heat radiation plate instead of the insulating substrate, the patent separates the structural modification needed for shrinkage suppression from the insulating substrate, thereby preserving its insulation performance while achieving the desired shrinkage cavity suppression effect.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The heat radiation plate serves as an intermediary structure that absorbs the mechanical stress and shrinkage forces. The dimples formed on the heat radiation plate act as a mediator to accommodate the bonding material shrinkage, preventing direct transmission of shrinkage forces to the insulating substrate and eliminating the need for dimples on the substrate itself.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If dimples are formed on the insulating substrate to suppress shrinkage cavity, then shrinkage cavity is suppressed, but the semiconductor element must be placed away from the outer periphery which impairs layout design freedom

Engineering Contradiction:
Improveshrinkage cavity suppressionVSAvoidlayout design freedom
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The invention extracts the shrinkage cavity suppression function from the insulating substrate and relocates it to the heat radiation plate. By forming dimples on the heat radiation plate instead of the insulating substrate, the patent separates the structural modification needed for shrinkage suppression from the insulating substrate, thereby preserving layout design freedom while achieving the desired shrinkage cavity suppression effect.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If bonding material containing elements with different solidification points is used, then bonding performance is improved, but shrinkage cavity and cracking occur during solidification

Engineering Contradiction:
Improvebonding performanceVSAvoidshrinkage cavity and cracking
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The invention changes the physical parameters of the bonding material by selecting elements with specific solidification points that create a controlled solidification sequence. The bonding material contains elements that solidify at different temperatures, allowing the first element to solidify and provide structural support before the second element solidifies, thereby preventing shrinkage cavity formation while maintaining good bonding performance.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively suppresses shrinkage cavity formation, maintains insulation performance, and enhances design flexibility by preventing dimple formation, ensuring reliable wire bonding and improved thermal stress resistance.

Implementation Method 1

When the solidification points of the plurality of elements contained in a bonding material are different, and an element solidified earlier is pulled by metal solidified later to generate a crack. This phenomenon is called a shrinkage cavity.

Methodology Applied
Scientific EffectSolidification: Freezing

Implementation Method 2

the interfacial tension occurs in the bonding material in contact with the heat radiation plate and the metal wire is a force toward the opposite direction to the shrinkage force of the bonding material that stretches the shrinkage cavity

Methodology Applied
Scientific EffectInterfacial tension: Surface Tension

Data Source

PatentUS11387352B2Power semiconductor device and manufacturing method thereof
Publication Date: 2022.07.12 MITSUBISHI ELECTRIC CORP
  • US11387352B2 patent drawing
  • US11387352B2 patent drawing
  • US11387352B2 patent drawing

AI summary

An object of the present disclosure is to suppress a shrinkage cavity without affecting the layout or the insulation performance of the semiconductor element in a power semiconductor device. A power semiconductor device includes a heat radiation plate; an insulating substrate bonded in a bonding region on an upper surface of the heat radiation plate with a bonding material containing a plurality of elements having different solidification points; a semiconductor element mounted on an upper surface of the insulating substrate; and a bonding wire bonded in the bonding region on the upper surface of the heat radiation plate such that the bonding wire surrounds the semiconductor element in plan view.