Power Semiconductor Device Spacer Alignment
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Solution Overview
Problem
The integration of semiconductor devices is hindered by the difficulty in forming contacts over source polysilicon layers in split gate trenches due to strict alignment and critical dimension requirements, leading to increased manufacturing costs and inconsistent gate polysilicon layers, which affect the electrical performance of power semiconductor devices.
Innovation Solution
A method involving the formation of trenches, sequential deposition and etching of oxide and polysilicon layers, and the use of spacers to facilitate direct contact formation above the source polysilicon layer, eliminating the need for specialized photomasks and protecting the gate polysilicon layer from ion implantation, thereby improving electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a dedicated photomask is used to define a predetermined area for contact formation over source polysilicon layer, then alignment precision and critical dimension control are improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The source polysilicon layer is formed to protrude beyond the trench surface in advance, creating a pre-positioned alignment reference structure. This preliminary action eliminates the need for dedicated photomasks during subsequent contact formation, as the protruding source polysilicon layer itself serves as the alignment guide, thereby reducing device complexity while maintaining manufacturing precision
Solution Approach 2:
The source polysilicon layer performs dual functions: it serves as both the functional source region and as a self-aligned reference structure for contact formation. By making the source polysilicon layer protrude, the structure serves itself as an alignment guide, eliminating the need for external photomask definitions and reducing overall device complexity
2Ease of manufacture
If the gate polysilicon layer is formed using conventional methods, then manufacturing process is simplified, but the gate polysilicon layer consistency deteriorates, adversely affecting electrical performance
Solution Approach 1:
The oxide layer thickness is made non-uniform with different thicknesses at different locations: a first thickness over the source polysilicon layer and a second thickness over the gate polysilicon layer. This local quality differentiation enables selective etching and deposition processes that ensure consistent gate polysilicon layer formation while maintaining ease of manufacture through standard semiconductor processing techniques
Solution Approach 2:
The solution introduces a vertical dimension variation through non-uniform oxide layer thickness to control the horizontal formation characteristics of the gate polysilicon layer. By controlling oxide thickness in the vertical dimension, the process achieves consistent gate polysilicon layer dimensions and properties, improving reliability while using conventional manufacturing methods
3Ease of manufacture
If ion implantation is performed without protecting the gate polysilicon layer, then source formation is simplified, but ion diffusion into the gate polysilicon layer occurs, degrading electrical performance
Solution Approach 1:
A spacer structure is introduced as an intermediary protective layer between the ion implantation source and the gate polysilicon layer. The spacer acts as a physical barrier that prevents ion diffusion into the gate polysilicon layer during source formation, thereby protecting electrical performance while allowing the ion implantation process to proceed using standard manufacturing techniques
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method reduces manufacturing costs, enhances circuit integration, and improves the electrical performance of power semiconductor devices by allowing direct contact formation and preventing ion diffusion into the gate polysilicon layer, thus increasing the threshold voltage and reducing fabrication complexities.
Implementation Method 1
performing, with the spacers serving as a mask, an implantation process to form a source in the semiconductor substrate adjacent to the trench
Implementation Method 2
forming a second oxide layer and a gate polysilicon layer, the second oxide layer covering both the exposed portion of the source polysilicon layer and the exposed portion of the inner surface of the trench
Data Source
AI summary
A power semiconductor device and a method of fabricating such a power semiconductor device are disclosed. In the method, spacers are formed, which cover sidewalls of a source polysilicon layer and reside on trench portions around the source polysilicon layer. As such, a contact is allowed to be directly formed above the source polysilicon layer, eliminating the need for a special photomask for defining a connection between the contact and the gate electrode, reducing the number of required steps, lowering the process cost and avoiding the risk of contact of the subsequently-formed contact above the source polysilicon layer with a gate polysilicon layer. With the spacers protecting a second oxide layer, during the subsequent formation of a source electrode, the implantation of some n-type ions into the second oxide layer, which may degrade the properties of the second oxide layer, is prevented.