Power Semiconductor Device Surge Protection via Segmented Barrier Layer
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Solution Overview
Problem
Power semiconductor devices face challenges in withstanding high voltage and large current during switching operations, leading to potential gate insulation film destruction due to displacement currents and voltage differences across the p-type barrier layer.
Innovation Solution
The design includes a second conductive type sense outer-peripheral well surrounding sense wells, a capacitor lower electrode region, and a gate insulation film, which operate together to increase capacitance and mitigate electric fields during static electricity exposure, thereby suppressing dielectric breakdown.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type barrier layer is formed under the gate electrode to increase transistor capacitance and improve surge resistance, then surge resistance is improved, but displacement current during switching generates large voltage differences that can destroy the gate insulation film
Solution Approach 1:
The barrier layer is segmented into two distinct regions: a first barrier layer region under the gate electrode with smaller area, and a second barrier layer region in the source region with larger area. This segmentation allows the first region to minimize displacement current and voltage buildup under the gate, while the second region provides sufficient capacitance for surge protection in the source region.
Solution Approach 2:
Different regions of the barrier layer are given different properties: the first barrier layer region under the gate electrode has optimized dimensions to reduce displacement current effects, while the second barrier layer region in the source region has larger area to provide the necessary capacitance for surge resistance. This local differentiation resolves the contradiction between surge protection and gate film safety.
2Reliability
If the sense cell transistor capacitance is made large to improve surge resistance, then surge resistance is improved, but the device complexity increases due to additional structures
Solution Approach 1:
The barrier layer structure serves multiple functions: it provides surge protection through capacitance in the source region, maintains gate insulation film safety by minimizing displacement current under the gate, and integrates seamlessly with the existing sense cell and main cell structures. The dual-region barrier layer performs both protective and functional roles without adding significant complexity.
Solution Approach 2:
The barrier layer is merged with the existing semiconductor structure, forming an integrated solution where the first and second barrier layer regions are part of the same continuous layer. This merging approach provides surge protection functionality without requiring separate discrete components or complex additional structures.
3Reliability
If a large-area detection source electrode is formed to create a large-capacitance parasitic capacitor for surge resistance, then surge resistance is improved, but the area occupied by the sense cell increases reducing electric efficiency
Solution Approach 1:
The barrier layer capacitance is concentrated in the source region where it is most needed for surge protection, rather than uniformly distributing it across the entire sense cell. The first barrier layer region under the gate maintains minimal area to preserve electric efficiency, while the second barrier layer region in the source region provides the necessary capacitance for surge resistance.
Solution Approach 2:
The capacitance-providing function is segmented and localized to the source region through the second barrier layer region, separating it from the gate electrode area. This segmentation allows the sense cell to maintain high electric efficiency in the active region while providing sufficient surge protection capacitance in the source region where it is most effective.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the device's ability to perform stable switching operations while providing high resistance to surges and reducing the risk of gate insulation film damage.
Implementation Method 1
a large capacitance parasitic capacitor is formed by a thin gate insulation film sandwiched between a large-area gate electrode arranged under a detection source electrode and a p-type barrier layer
Data Source
AI summary
A power semiconductor device includes a second conductive type sense outer-peripheral well formed to surround a plurality of sense wells on the surface of a drift layer, a first conductive type main-cell source region selectively formed on the surface of the main cell well, a first conductive type sense source region selectively formed on the surface of the sense well, a first conductive type capacitor lower electrode region selectively formed on the surface of the sense outer-peripheral well, a gate insulation film formed on the channel regions and on the sense outer-peripheral well, a gate electrode formed on the gate insulation film, and a sense pad electrically connected to the sense well and the sense source region as well as on the sense outer-peripheral well and the capacitor lower electrode region.