Power Semiconductor Device Thick Top-Metal Design
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Solution Overview
Problem
Existing power semiconductor devices face challenges in achieving a balance between low on-state voltage and high blocking capability due to inhomogeneous wafer thickness caused by the grinding process, which affects the device's ruggedness and performance.
Innovation Solution
The method involves forming a metallization layer in two steps, with a lower portion before and an upper portion after the isolation layer formation, to ensure uniform thinning and maintain the thickness of the termination area relative to the active cell area, using a polyimide isolation layer with a thickness of 5 μm or more to reduce the impact of metal particles on electric field distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the wafer thickness is reduced to minimize losses and improve switching speeds, then the on-state voltage and losses are reduced, but the blocking capability and ruggedness deteriorate
Solution Approach 1:
The patent applies local quality by creating different wafer thicknesses in different regions: the termination area is maintained at a greater thickness than the active cell area. This is achieved by forming a metallization layer that extends beyond the isolation layer in the active cell area, creating a height difference that prevents excessive thinning during the grinding process. The termination area thus retains sufficient thickness for blocking capability while the active cell area can be thinned to reduce losses.
2Loss of energy
If the wafer is uniformly ground to reduce thickness, then the on-state voltage is reduced, but the thickness in the termination area becomes insufficient, compromising blocking capability
Solution Approach 1:
The patent implements local quality by making the metallization layer thickness non-uniform across different areas. The metallization layer is formed to be thicker in the active cell area than in the termination area, creating a height difference that translates to different final thicknesses after grinding. This allows the active cell area to achieve the desired thinness for low on-state voltage while the termination area maintains sufficient thickness.
Solution Approach 2:
The patent applies preliminary action by forming the metallization layer with extended thickness in the active cell area before the grinding process. This pre-established height difference ensures that during subsequent uniform grinding, the active cell area starts with more material to remove, resulting in the desired thickness variation in the final product without requiring complex non-uniform grinding processes.
3Device complexity
If a thin isolation layer is used, then the device complexity is reduced, but metal particles affect electric field distribution, compromising reliability
Solution Approach 1:
The patent uses the metallization layer as an intermediary element that serves multiple functions. It not only provides electrical connection but also acts as a thickness-compensating structure during grinding and as a protective layer that prevents metal particles from disrupting the electric field distribution in the isolation layer. The metallization layer's extended formation in the active cell area creates the necessary height difference while maintaining overall structural integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the blocking capability and ruggedness of the power semiconductor device while maintaining a low on-state voltage, ensuring homogeneous wafer thickness and reliability by minimizing the influence of metal particles on electric field distribution.
Implementation Method 1
the back surface of the n-type wafer is uniformly ground for reducing the thickness of the n-type wafer
Data Source
AI summary
The present application contemplates a method for manufacturing a power semiconductor device. The method comprises: providing a wafer of a first conductivity type, the wafer having a first main side and a second main side opposite to the first main side, and the wafer including an active cell area, which extends from the first main side to the second main side, in a central part of the wafer and a termination area surrounding the active cell area in an orthogonal projection onto a plane parallel to the first main side; forming a metallization layer on the first main side to electrically contact the wafer in the active cell area, wherein the surface of the metallization layer, which faces away from the wafer, defines a first plane parallel to the first main side; forming an isolation layer on the first main side in the termination area, wherein the surface of the isolation layer facing away from the wafer defines a second plane parallel to the first main side; after the step of forming the metallization layer and after the step of forming the isolation layer, mounting the wafer with its first main side to a flat surface of a chuck; and thereafter thinning the wafer from its second main side by grinding while pressing the second main side of the wafer onto a grinding wheel by applying a pressure between the chuck and the grinding wheel, wherein the first plane is further away from the wafer than a third plane, which is parallel to the second plane and arranged at a distance of 1 μm from the second plane in a direction towards the wafer.