Power Semiconductor Device with Varying Dopant Dose Profiles

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Solution Overview

Problem

Power semiconductor devices face challenges in achieving a reliable and efficient load current distribution, particularly in preventing overheating and dynamic avalanche, due to uneven load current density and temperature distribution within the semiconductor body.

Innovation Solution

The implementation of frontside and/or backside emitters with strategically designed lateral and vertical dopant dose profiles in the peripheral volumes adjacent to the edge termination region, ensuring a controlled load current density distribution by varying the dopant doses in the central, peripheral, and edge regions of the semiconductor device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a uniform dopant dose is applied across the semiconductor body, then the manufacturing process is simple, but the load current density distribution becomes uneven causing overheating and dynamic avalanche

Engineering Contradiction:
Improvedevice reliabilityVSAvoiddopant dose profile complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different dopant doses to different regions of the semiconductor body: a first dopant dose for the central region and a second dopant dose for the peripheral region. This local differentiation creates a non-uniform dopant dose profile that specifically addresses the load current density distribution issue in peripheral areas without complicating the entire device structure, thereby improving reliability while maintaining manageable complexity

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The semiconductor body is segmented into distinct regions (central region and peripheral region) with different dopant dosing characteristics. This segmentation allows independent optimization of each region's electrical properties, enabling better load current density control in the peripheral area while maintaining overall device functionality

Inventive Principle:
Principle #1Segmentation

2Productivity

If the peripheral volume has high load current density, then the current conduction capability is improved, but overheating and dynamic avalanche occur

Engineering Contradiction:
Improvecurrent conduction capabilityVSAvoidtemperature distribution
Core Design Contradiction:
ProductivityVSTemperature

Solution Approach 1:

The patent implements a locally optimized dopant dose profile where the peripheral region receives a specific dopant dose (second dopant dose) that is tailored to control the load current density in that specific area. This local quality adjustment ensures adequate current conduction capability while preventing excessive current density that would lead to overheating and dynamic avalanche

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach allows for a more uniform load current distribution and reduced risk of overheating, enhancing the reliability and efficiency of power semiconductor devices by managing load current density and temperature distribution effectively.

Implementation Method 1

At least one of the first doped semiconductor region and the second doped semiconductor region has a central portion extending into the central volume of the active region and having a central average dopant dose; a peripheral portion extending into the peripheral volume of the active region and having a peripheral average dopant dose

Methodology Applied
Scientific EffectDopant dose gradient: Diffusion

Data Source

PatentUS20200357883A1Power Semiconductor Device and Method
Publication Date: 2020.11.12 INFINEON TECHNOLOGIES AG
  • US20200357883A1 patent drawing
  • US20200357883A1 patent drawing
  • US20200357883A1 patent drawing

AI summary

A power semiconductor device includes an active region having a total volume with a central volume forming at least 20% of the total volume, a peripheral volume forming at least 20% of the total volume and surrounding the central volume, and an outermost peripheral volume forming at least 5% of the total volume and surrounding the peripheral volume. The peripheral volume has a constant lateral distance from an edge termination region. A first doped semiconductor region is electrically connected with a first load terminal at a semiconductor body frontside. A second doped semiconductor region is electrically connected with a second load terminal at a semiconductor body backside. The first and/or second doped semiconductor region has: a central portion extending into the central volume and having a central average dopant dose; and a peripheral portion extending into the peripheral volume and having a peripheral average dopant dose.