Detecting Power Sequence Risks in Multi-Rail Circuits
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Solution Overview
Problem
Existing methods for evaluating electronic circuit designs are inadequate in identifying power sequence risks, particularly for complex circuits with multiple independent DC power rails, leading to issues like latch-up, current leakage, and unexpected power consumption due to parasitic diodes, which can result in unrecoverable states and chip damage.
Innovation Solution
A computerized method that analyzes the topology of electronic circuits to automatically detect power sequence risks by tracing DC power paths, identifying parasitic diodes, and generating dependency graphs to report problematic power sequences, without requiring users to anticipate all possible power sequences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional circuit simulation methods are used to evaluate power sequence risks, then the analysis can be performed on specific IC design structures, but the method requires users to anticipate and input all possible power sequences, which is impractical for complex circuits with multiple independent power rails
Solution Approach 1:
The circuit design itself provides the analysis results by automatically generating power sequence risk information through logical evaluation of its own structure. The method extracts power rail relationships and potential risk scenarios directly from the circuit netlist without requiring external input of test sequences, making the circuit structure serve the analysis purpose.
Solution Approach 2:
The method performs preliminary logical evaluation of the circuit structure to identify potential power sequence risks before actual circuit operation or detailed simulation. By analyzing the circuit topology and power rail dependencies in advance, the method prepares risk information that guides subsequent simulation or design decisions.
2Reliability
If comprehensive power sequence testing is performed to identify all potential risks, then reliability can be improved, but the time and computational resources required increase significantly
Solution Approach 1:
The method performs preliminary logical evaluation of the circuit structure to identify potential power sequence risks before actual circuit operation or detailed simulation. By analyzing the circuit topology and power rail dependencies in advance, the method prepares risk information that guides subsequent simulation or design decisions, avoiding exhaustive testing.
Solution Approach 2:
The method focuses on evaluating logical power sequence risks based on circuit structure rather than performing exhaustive simulation of all possible power sequences. This partial evaluation approach identifies the most critical risks without requiring complete testing of every scenario, reducing time while maintaining reliability assessment quality.
3Measurement precision
If parasitic diodes are included in circuit simulations to accurately model real behavior, then measurement precision improves, but the simulation complexity and computational burden increase
Solution Approach 1:
The method extracts and separately evaluates the power sequence risk information from the circuit structure without requiring full inclusion of parasitic diode models in the simulation. By isolating the logical risk assessment from the detailed physical simulation, the method achieves accurate risk identification while maintaining simulation simplicity.
Solution Approach 2:
The analysis is segmented into two parts: logical power sequence risk evaluation based on circuit topology, and separate detailed simulation if needed. This segmentation allows the method to address power sequence risks without requiring complex parasitic diode modeling in the main simulation flow.
Data Source
AI summary
An automated method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The method operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The invention inspects the various devices and automatically traces DC circuit paths to DC power rails. The invention then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The method generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.