Detecting Power Sequence Risks in Complex Circuit Topologies
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Solution Overview
Problem
Existing methods for evaluating electronic circuit designs are inadequate in identifying power sequencing risks, particularly for complex circuits with multiple independent DC power rails, as they require anticipating all possible power sequences and are poorly suited to detect issues caused by unexpected power-up or power-down sequences, leading to reliability problems such as latch-up and unintended current drain.
Innovation Solution
A computerized method that analyzes the circuit topology to automatically identify power sequence risks by tracing DC power paths, determining the existence and connectivity of parasitic diodes, and generating power dependency graphs, allowing for the detection of problematic power sequences without requiring user input of all possible scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional circuit simulation methods are used to evaluate power sequencing risks, then the analysis can be performed with existing tools, but the methods fail to automatically identify all problematic power sequences in complex circuits with multiple independent DC power rails
Solution Approach 1:
The patent segments the complex circuit analysis into manageable components by identifying and analyzing individual DC power paths separately. The method breaks down the circuit topology into discrete power paths connecting DC power rails to ground, allowing systematic evaluation of each path's behavior under different power sequences without being overwhelmed by the overall circuit complexity.
Solution Approach 2:
The patent performs preliminary analysis by automatically tracing and identifying all DC power paths and parasitic diodes before evaluating power sequencing risks. This preliminary action of mapping the circuit topology and pre-identifying potential risk locations enables the subsequent power sequence analysis to be more efficient and comprehensive, addressing the complexity issue by preparing the analysis framework in advance.
2Reliability
If manual identification of all possible power sequences is attempted, then comprehensive coverage can be achieved, but the process becomes impractical and time-consuming for complex circuits
Solution Approach 1:
The patent implements self-service by automating the identification and evaluation of power sequences through computerized analysis. The system automatically traces DC power paths, identifies parasitic diodes, and evaluates power sequencing risks without requiring manual enumeration of all possible sequences. This automation eliminates the time-consuming manual process while maintaining comprehensive coverage of potential power sequence risks.
Solution Approach 2:
The patent changes the analysis approach from manual sequence-by-sequence evaluation to automated parameter-based analysis. By using computerized methods to systematically vary power rail states and evaluate circuit behavior, the patent transforms the time-intensive manual process into an efficient automated parameter sweep that comprehensively covers all possible power sequences.
3Reliability
If circuit designs are optimized to prevent parasitic diode conduction, then reliability improves, but the design flexibility and performance optimization are constrained
Solution Approach 1:
The patent applies preliminary action by performing power sequence risk analysis during the design phase before finalizing the circuit implementation. By automatically identifying potential parasitic diode conduction paths and power sequencing risks early in the design process, engineers can make informed decisions about circuit topology and power management strategies, maintaining design flexibility while ensuring reliability.
Solution Approach 2:
The patent implements feedback by providing automated analysis results that inform design decisions. The computerized identification of power sequence risks and parasitic diode behaviors feeds back to the design process, allowing engineers to iteratively optimize circuit designs to prevent unwanted conduction while maintaining performance and flexibility. This feedback loop enables continuous improvement without rigid constraints.
Data Source
AI summary
An automated system and method of determining power sequencing risks (e.g. power-up, power-down time sequences) for complex computer circuits with multiple independent power supplies. The system operates by logical consideration of the topological arrangement of MOSFETs and other devices in standard netlists. The system inspects the various devices and automatically traces DC circuit paths to DC power rails. The system then evaluates, as a type of logical existence proof, and on a per MOSFET device level, if due to assignment to different DC power levels, various factors, such as forward-biased diodes, floating MOSFET gate, and other risk factors could ever occur. The system generates comprehensive records of such risks and can output an overall analysis of a circuit reporting on both problematic power sequences, as well as circuit design factors that may be sub-optimal from a power sequence perspective.