Power Sequencing for Inrush Current Management

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Solution Overview

Problem

Existing power management systems in electronic devices face challenges in managing inrush currents when multiple components are powered on simultaneously, leading to potential exceeding of design limits and increased latency due to uniform or staggered power-on procedures.

Innovation Solution

A power sequencing method that maintains sequencing information for operational elements, prioritizing and delaying power-on requests to avoid inrush current spikes, allowing user-programmable sequencing and timings to establish relative priorities and inrush delays, thereby reducing power system component size and latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If multiple components are powered on simultaneously, then power-on time is reduced, but inrush current exceeds design limits

Engineering Contradiction:
Improvepower-on timeVSAvoidinrush current
Core Design Contradiction:
Loss of timeVSObject-affected harmful factors

Solution Approach 1:

The system pre-establishes a power sequencing table that defines the priority order and timing for powering on different components. Before actual power-on occurs, the controller references this pre-defined sequence to activate components in a controlled manner, preventing simultaneous power-on while maintaining efficient startup timing.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The power sequencing mechanism dynamically adjusts the power-on timing of individual components based on their priority levels and inrush current characteristics. The controller modulates the power delivery timing to balance between reducing total power-on time and limiting peak inrush current, creating an adaptive power-on strategy.

Inventive Principle:
Principle #15Dynamics

2Object-affected harmful factors

If uniform power-on delay is applied to all components, then inrush current is limited, but power-on latency increases

Engineering Contradiction:
Improveinrush currentVSAvoidpower-on latency
Core Design Contradiction:
Object-affected harmful factorsVSLoss of time

Solution Approach 1:

Instead of applying a uniform power-on delay to all components, the system assigns different delay characteristics to different components based on their individual priorities and inrush current profiles. Critical components with low inrush current can be powered on with minimal or no delay, while components with high inrush current receive appropriate delays, creating a customized power-on strategy for each component.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The power-on process is segmented into multiple priority levels and time slots. Rather than treating all components equally with a single delay parameter, the system divides components into groups based on their power-on characteristics and applies differentiated timing strategies to each group, optimizing the overall power-on sequence.

Inventive Principle:
Principle #1Segmentation

3Object-affected harmful factors

If larger power supply components are used, then inrush current capacity is increased, but device size and power consumption increase

Engineering Contradiction:
Improveinrush current capacityVSAvoidpower system component size
Core Design Contradiction:
Object-affected harmful factorsVSWeight of stationary object

Solution Approach 1:

The system pre-characterizes each component's inrush current profile and stores this information in a power sequencing table. Before power-on, the controller uses this pre-collected data to calculate and implement an optimized power sequence that keeps peak current within the capabilities of smaller, more efficient power supply components, eliminating the need for oversized power supplies.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3519917B1Prioritized sequencing of device inrush current
Publication Date: 2022.03.09 MICROSOFT TECHNOLOGY LICENSING LLC
  • EP3519917B1 patent drawingFigure 1
  • EP3519917B1 patent drawingFigure 2
  • EP3519917B1 patent drawingFigure 3

AI summary

Input power sequencing implementations for electronic, processing, and computing systems are presented herein. In one example, a method of providing power to operational elements of an electronic system is provided. The method includes maintaining sequencing information for the operational elements that indicates relative priorities and inrush delays for each of the operational elements. Responsive to ones of the operational elements requesting transition to a powered state, the method includes placing at least indications of the ones of the operational elements into a queue, establishing a power sequencing process for servicing the queue based at least on the sequencing information associated with the operational elements in the queue, and initiating the power sequencing process to provide input power to the operational elements in the queue.