Power Shared Cell Architecture for Sub-10nm ICs
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Solution Overview
Problem
As integrated circuits scale to smaller features, conventional fabrication processes face challenges in achieving higher performance due to increased variability and the need for tighter metal pitches, which limits the ability to extend into sub-10 nm technology nodes without new methodologies or integrated technologies.
Innovation Solution
A power shared track cell architecture is introduced, where power tracks are segmented into power and signal segments within the cell, allowing the same track to be used for both power and signals, reducing the number of tracks needed and enabling higher cell density without requiring tighter pitches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used with dedicated power tracks, then manufacturing simplicity is maintained, but manufacturing precision deteriorates due to variability limits at 10 nm or sub-10 nm nodes
Solution Approach 1:
The patent merges power and signal tracks into a shared track structure. The power shared track cell architecture allows a single track to serve dual purposes: carrying power during certain phases and carrying signals during other phases. This consolidation reduces the number of separate tracks needed, thereby improving manufacturing precision by reducing variability associated with multiple tight-pitch tracks while maintaining ease of manufacture through a unified track design.
Solution Approach 2:
The patent implements dynamic track assignment where the function of each track changes over time. Tracks are dynamically allocated to carry power or signals based on operational phases. This dynamic approach allows the same physical infrastructure to adapt to different functional requirements, improving manufacturing precision by reducing static structural complexity while maintaining fabrication simplicity through a standardized dynamic track system.
2Quantity of substance
If metal pitch is reduced to increase cell density, then cell density improves, but device complexity increases due to tighter pitch constraints
Solution Approach 1:
By merging power and signal functions into shared tracks, the patent reduces the total number of tracks required in the cell. This consolidation increases cell density without requiring proportionally tighter pitch constraints, as fewer tracks need to be routed at minimum spacing. The shared track architecture achieves higher density while managing pitch complexity through functional multiplexing rather than purely spatial compression.
Solution Approach 2:
The patent creates universal tracks that can serve multiple functions (power or signal) depending on operational context. This multi-functionality allows the same track infrastructure to support higher cell density without proportionally increasing pitch complexity, as the tracks are not dedicated to single functions requiring strict spacing. The universal track design enables flexible resource allocation that optimizes density while controlling routing complexity.
3Reliability
If dedicated power tracks are used on the first metal level, then power delivery reliability is ensured, but area utilization deteriorates due to reduced space for signal routing
Solution Approach 1:
The patent merges power and signal track functions into shared tracks, eliminating the need for separate dedicated power tracks on the first metal level. This consolidation frees up area previously occupied by dedicated power tracks, allowing for more efficient signal routing and reduced cell footprint. Power delivery reliability is maintained through the shared track architecture that provides sufficient power capacity while optimizing spatial utilization.
Solution Approach 2:
The patent transitions from a spatial separation approach (dedicated power tracks occupying specific areas) to a temporal separation approach (power and signals using the same track at different times). This dimensional shift from space to time allows power delivery reliability to be maintained without sacrificing area utilization, as the same physical space is reused dynamically for different functions based on operational requirements.
Data Source
AI summary
An integrated circuit structure includes a metal level comprising a plurality of interconnect lines along a first direction. A cell is on the metal level, wherein one or more of the plurality of interconnect lines that extend through the cell comprise a power shared track that is segmented inside the cell into one or more power segments and one or more signal segments so that both power and signals share a same track.