Power Surface-Mount Device Package with Variable Solder Bumps
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Solution Overview
Problem
Conventional flip chip packaging techniques are hindered in power packages due to smaller solder bumps' inability to carry high currents and larger bumps' incompatibility with high-speed signal lines, leading to real estate issues and inappropriate use in power packages.
Innovation Solution
Formation of solder bumps of different sizes and shapes on a single die, where larger bumps can carry higher currents and smaller bumps are suitable for signal lines, with both having approximately the same height to ensure even mounting and connections after reflowing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If smaller solder bumps are used for flip chip mounting, then high-speed signal line compatibility is improved, but current carrying capacity deteriorates
Solution Approach 1:
The patent applies local quality by creating different solder bump sizes at different locations on the die. Larger solder bumps are formed over power/ground bond pads to handle high currents, while smaller solder bumps are formed over signal bond pads to maintain high-speed signal integrity. This spatial variation in solder bump properties resolves the contradiction between signal speed and current carrying capacity.
2Reliability
If larger solder bumps are used to carry higher currents, then power line current capacity is improved, but compatibility with high-speed signal lines deteriorates
Solution Approach 1:
The patent implements local quality by varying solder bump dimensions according to the functional requirements of different bond pads. Power and ground bond pads receive larger solder bumps optimized for current carrying, while signal bond pads receive smaller solder bumps optimized for high-speed performance. This localized differentiation eliminates the need to compromise either current capacity or signal speed.
3Ease of manufacture
If uniform solder bump sizes are used on all bond pads, then manufacturing simplicity is improved, but performance optimization for different signal types deteriorates
Solution Approach 1:
The patent resolves this contradiction by making solder bump properties location-dependent rather than uniform. The manufacturing process is configured to deposit solder material in varying quantities at different bond pad locations, creating larger bumps for power/ground connections and smaller bumps for signal connections. This approach maintains manufacturing feasibility while achieving performance optimization for different signal types.
4Adaptability or versatility
If different sized solder bumps are formed on a single die, then power package performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies parameter changes by modifying the solder deposition parameters (such as solder paste quantity, screen opening sizes, or reflow conditions) to create different solder bump dimensions at different locations on the same die. This allows the manufacturing process to produce varied solder bump sizes using standard surface mount techniques, achieving power package performance without excessive manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient electrical connections for power and signal lines with consistent height, accommodating the unique requirements of power packages while maintaining even die mounting on substrates.
Implementation Method 1
When the resulting die is mounted on a substrate or other appropriate carrier, the solder bumps may be reflowed to create electrical connections to the die
Data Source
AI summary
A semiconductor device is provided, which comprises: a die including an active surface; a multiplicity of bond pads formed on the active surface of the die, wherein a first one of the bond pads is larger than a second one of the bond pads; and a multiplicity of solder bumps, each formed over a corresponding bond pad, wherein the multiplicity of solder bumps include a first solder bump formed over the first bond pad and a second solder bump formed over the second bond pad, the first solder bump having a footprint that is substantially larger than the second solder bump and a maximum diameter that is substantially larger than the second solder bump.