Power Stage Input Discharge Circuit for High-Side FET Startup
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Solution Overview
Problem
In modern high-current converters, the gate driver of the high-side FET is not directly provided with the input voltage, leading to a significant delay in discharging the gate capacitance, resulting in partial turn-on of the high-side FET and excessive inductor current, which can increase the output voltage above its desired value.
Innovation Solution
A circuit incorporating a current mirror, diodes, and a discharge transistor, along with a startup module that generates a fast startup discharge signal to quickly discharge the high-side FET gate, using a slow control voltage to regulate and stabilize the supply rails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate driver is connected to VIN through an RC filter and supply disconnect switch (or regulated/clamped power rail), then the internal voltage is protected from exceeding maximum voltage, but there is a significant delay before the internal voltage rises enough to discharge the high-side FET gate
Solution Approach 1:
The startup module generates a fast startup discharge signal that activates the discharge transistor before the internal regulated voltage rail becomes sufficient to discharge the gate. This preliminary action removes the harmful gate charge accumulation that would otherwise occur during the delay period, allowing the RC filter or voltage regulator to subsequently provide reliable voltage protection without causing gate discharge delays.
2Reliability
If the internal voltage rises slowly due to RC filter or voltage regulation, then the internal voltage remains protected within maximum limits, but the high-side FET experiences partial turn-on producing excessive inductor current
Solution Approach 1:
The discharge transistor is activated by the fast startup discharge signal to create a discharge path for the gate capacitance before the internal voltage rises. This preliminary anti-action counteracts the potential harmful effect of gate charge accumulation that would cause partial FET turn-on and excessive inductor current, while allowing the voltage regulation mechanism to subsequently maintain reliable voltage protection.
3Speed
If the discharge transistor gate is connected directly to the fast startup signal, then rapid discharge is achieved, but the discharge signal may exceed maximum specified supply voltage
Solution Approach 1:
The fourth FET acts as an intermediary between the fast startup signal and the discharge transistor gate. It transfers the fast rising edge of the startup signal to the discharge transistor gate while its source terminal and associated diode structure limit the maximum voltage to stay below the specified supply voltage maximum, thus achieving both rapid discharge and voltage protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures rapid discharge of the high-side FET gate capacitance, preventing excessive inductor current and maintaining the output voltage within desired limits by closely tracking the supply voltage rise.
Implementation Method 1
The first diode is connected in series between the second drain and the ground, and the first diode is configured to limit the fast startup signal to a first maximum voltage less than a maximum specified supply voltage
Implementation Method 2
The second diode is connected in series between the fourth source and the ground, and the second diode is configured to limit the startup discharge signal to a second maximum voltage less than the maximum specified supply voltage
Implementation Method 3
a discharge transistor configured to discharge the gate of the high-side FET in response to the startup discharge signal
Data Source
AI summary
A circuit for controlling a discharge transistor for a power stage includes a current mirror, a first diode, and a second diode. The current mirror includes first, second, third and fourth field-effect transistors (FETs) configured to provide a fast startup signal and a startup discharge signal. The startup discharge signal is provided to a gate of the discharge transistor. The first diode is configured to limit the fast startup signal to a first maximum voltage less than the supply voltage, and the second diode is configured to limit the startup discharge signal to a second maximum voltage less than the supply voltage.