Power Semiconductor Submodule Layout for Low-Inductance Assembly
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Solution Overview
Problem
The challenge is to improve the productivity of power semiconductor devices while minimizing the increase in main circuit inductance, which is essential for reducing surge voltage and enhancing heat dissipation in high-power density applications.
Innovation Solution
The solution involves a power semiconductor device design with a first and second submodule, where the second submodule's electrode surfaces are inverted, and a signal relay conductor is used to connect the submodules to signal terminals, reducing inductance and improving manufacturing efficiency by ensuring uniform terminal heights and alignment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If the single-arm power semiconductor element is inverted as in PTL 2, then main circuit inductance is reduced, but productivity of the power semiconductor device including upper and lower arms deteriorates
Solution Approach 1:
The power semiconductor device is divided into multiple independent modules (first module, second module, third module, fourth module), each containing power semiconductor elements with inverted electrode surfaces. This segmentation allows each module to be manufactured and assembled independently, improving productivity while maintaining the inductance-reducing inverted structure.
Solution Approach 2:
The power semiconductor elements in different modules have asymmetric arrangements where the electrode surfaces are inverted relative to each other. Specifically, the first and second power semiconductor elements have their electrode surfaces inverted, as do the third and fourth elements. This asymmetric inverted arrangement reduces main circuit inductance while the modular approach maintains productivity.
2Loss of energy
If switching speed is increased to reduce switching loss, then power density is improved, but surge voltage increases due to parasitic inductance
Solution Approach 1:
The asymmetric inverted arrangement of electrode surfaces in the power semiconductor elements creates opposing current paths that cancel out the magnetic fields generated by parasitic inductance. This reduces surge voltage effects, enabling higher switching speeds and improved power density without excessive voltage spikes.
Solution Approach 2:
The parasitic inductance that normally causes harmful surge voltage is converted into a beneficial effect through the inverted electrode arrangement. The magnetic fields from adjacent elements with inverted polarity oppose each other, canceling out the harmful surge voltage and allowing faster switching operations.
Data Source
AI summary
A power semiconductor device includes a first submodule including a first power semiconductor element, a second submodule including a second power semiconductor element, a positive electrode side conductor portion and a negative electrode side conductor portion, an intermediate substrate that forms a negative electrode side facing portion facing the negative electrode side conductor portion with the first submodule sandwiched between them and a positive electrode side facing portion facing the positive electrode side conductor portion with the second submodule sandwiched between them, and a plurality of signal terminals that transmit a signal for controlling the first power semiconductor element or the second power semiconductor element. The second submodule is disposed such that directions of an electrode surface of the second power semiconductor element and an electrode surface of the first power semiconductor element are inverted, a signal relay conductor portion is disposed in a space sandwiched between a part of the second submodule and the intermediate substrate in a height direction of the second submodule, and the intermediate substrate has a wire connected to the signal relay conductor portion and electrically connected to the signal terminal. In this manner, productivity of the power semiconductor device is improved while an increase in main circuit inductance is suppressed.