Power Substrate Assembly With Trimetal Clip to Limit DCB Warpage
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Solution Overview
Problem
Power substrates with DCB layers face warpage issues due to mismatched coefficients of thermal expansion (CTE) of components soldered onto the DCB surface, which can compromise solder connections and lead to substrate instability.
Innovation Solution
A power substrate assembly is designed to mitigate warpage by incorporating a clip and a trimetal structure, where the trimetal has a button array that mates with a cavity array in the clip, eliminating the need for solder between the clip and trimetal, and enhancing the substrate's resistance to warpage through modified ceramic tiles with improved thermal conductivity and strength.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If DCB layers are used in power substrates to provide good thermal conductivity, then thermal performance is improved, but warpage occurs due to CTE mismatch between components
Solution Approach 1:
The patent modifies the CTE parameters of the substrate by incorporating a CTE control layer with specific material composition and thickness. This layer is designed with a CTE value that bridges the mismatch between the DCB ceramic layer and the soldered components, thereby reducing warpage while preserving the thermal conductivity benefits of the DCB structure
Solution Approach 2:
The patent employs a composite substrate structure consisting of multiple layers including DCB ceramic, copper foil, and a specially designed CTE control layer. This composite construction allows each layer to contribute its specific properties: the DCB layer provides thermal conductivity, while the CTE control layer manages thermal expansion differences, collectively solving both thermal performance and warpage issues
2Reliability
If components are soldered onto DCB surface to form electrical circuits, then electrical connectivity is improved, but warpage increases due to CTE mismatch
Solution Approach 1:
The patent introduces a CTE control layer as an intermediary between the DCB ceramic surface and the soldered components. This intermediate layer acts as a buffer that absorbs the CTE mismatch stress, allowing reliable electrical connections to be formed on the DCB surface without transmitting warpage-inducing stresses to the substrate structure
3Reliability
If ceramic tile is used in power substrate to provide electrical isolation, then voltage isolation is improved, but warpage occurs due to thermal expansion mismatch
Solution Approach 1:
The patent modifies the thermal expansion parameters of the substrate assembly by inserting a CTE control layer adjacent to the ceramic tile. This layer's CTE is specifically engineered to match or bridge the difference between the ceramic tile and surrounding components, reducing warpage while preserving the electrical isolation properties of the ceramic
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The power substrate assembly effectively reduces the likelihood of warpage, maintains reliable connections, and enhances thermal performance and strength, thereby improving the overall stability and efficiency of power substrates.
Implementation Method 1
DCB warpage occurs when there is a mismatch of the coefficient of thermal expansion (CTE) of the components being soldered onto the DCB surface
Implementation Method 2
The base is soldered to the chip. The foot is connected to the power substrate
Implementation Method 3
Direct bonded copper (DBC), also known as direct copper bonded (DCB) substrates, have very good thermal conductivity, and are thus suitable for power modules
Data Source
Figure 1A~1B
Figure 2A~2E
AI summary
A substrate assembly may include a power substrate, a chip, a clip, and a trimetal. The power substrate has a first direct copper bonded (DCB) surface connected to a ceramic tile. The chip is soldered onto the first DCB surface. The clip is attached to the power substrate and has a foot at one end and a recessed area at the other, opposite end. The foot is connected to the power substrate. The trimetal has a base, a trapezoid structure, and a clip portion. The base is soldered to the chip. The trapezoid structure is located above the base. The clip portion is located above the trapezoid structure and includes a projecting area. The recessed area of the clip fits into the projecting area of the trimetal.