Power Semiconductor Substrate Layout for Heat and Wiring Reduction
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Solution Overview
Problem
Conventional semiconductor devices incorporating power switching elements like MOSFETs and IGBTs face challenges in efficiently converting DC to AC voltage while maintaining reliability and reducing costs, particularly in applications requiring high current handling and thermal management.
Innovation Solution
The semiconductor device employs a configuration with silicon carbide-based power semiconductor chips, a main substrate with copper-based conductive layers, and a sub-substrate structure that includes a sub-insulating layer flanked by sub-metal layers, allowing for improved electrical connectivity and thermal dissipation, along with a sealing resin to protect and integrate the components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a conventional semiconductor device structure with ceramic substrate and separate conductive layers is used, then electrical connectivity is achieved, but device complexity and manufacturing cost increase due to multiple discrete components and wiring
Solution Approach 1:
The patent combines the substrate and conductive layers into an integrated main substrate structure where copper-based conductive layers are formed directly on the insulating base member. This merging eliminates the need for separate ceramic substrates and discrete conductive layer assemblies, reducing device complexity while maintaining electrical connectivity through the integrated design
2Reliability
If additional wiring and thermal protection components are added to conventional semiconductor devices, then thermal management and electrical connectivity are improved, but manufacturing cost increases
Solution Approach 1:
The main substrate is designed to perform multiple functions simultaneously: it provides electrical insulation through its base member, conducts electricity through integrated copper-based conductive layers, and manages heat dissipation through thermally conductive pathways. This multi-functionality eliminates the need for separate thermal protection and wiring components, reducing manufacturing cost while maintaining thermal management capability
Solution Approach 2:
The patent employs composite material structures where copper-based conductive layers are integrated with insulating base members to create a main substrate that combines electrical conductivity, insulation, and thermal management properties in a single component, reducing the need for additional discrete thermal protection components
3Power
If silicon carbide-based power semiconductor chips are used, then power handling capability and efficiency are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies local quality by creating dedicated bonding regions on the main substrate with specific copper-based conductive layer configurations that optimize electrical and thermal contact with the silicon carbide chips. These localized structures provide precise alignment and contact areas, reducing overall manufacturing precision requirements while maintaining high power handling capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the conversion efficiency of DC to AC voltage, improves thermal management, and reduces costs by minimizing the need for additional wiring and thermal protection, thereby optimizing performance and reliability in high-current applications.
Implementation Method 1
the second sub-metal layer is electrically bonded to the first main metal layer
Implementation Method 2
improves thermal management
Data Source
AI summary
A semiconductor device includes: a main substrate including a first main metal layer; a first semiconductor element supported by the main substrate; a first sub-substrate supported by the main substrate; and a sealing resin covering the first semiconductor element. The first sub-substrate includes a sub-insulating layer, and a first sub-metal layer and a second sub-metal layer that flank the sub-insulating layer in a thickness direction. The second sub-metal layer is electrically bonded to the first main metal layer, and the first sub-metal layer includes a region. The first sub-substrate further includes a connecting conductive portion that electrically connects the region and the second sub-metal layer.