Power Semiconductor Substrate Layout to Minimize Solder Voids
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Solution Overview
Problem
The formation of voids during the soldering process in power semiconductor assemblies due to thermal expansion mismatch leads to reduced heat transfer and decreased performance and lifetime, primarily under power semiconductor elements.
Innovation Solution
Incorporating recesses and/or non-solderable coatings in the metal layer outside the contact surface of power semiconductor elements to control cavity formation, optimizing heat transfer by preventing vacuum formation during cooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the substrate is soldered to the base plate during system soldering, then a metallurgical bond is created for mechanical strength and electrical connection, but thermal expansion mismatch causes warping and vacuum formation leading to cavity (void) formation that reduces heat transfer
Solution Approach 1:
The invention applies a non-solderable coating (such as oxide layer, solder resist, or graphite layer) to specific regions of the metal layer on the substrate. This creates local differentiation where certain areas remain solderable (under power semiconductor elements) while other areas are made non-solderable (in regions where cavities would form). This local quality change prevents vacuum formation and cavity formation in critical heat transfer zones while maintaining mechanical bond strength in functional areas.
2Shape
If the substrate warps during heating and cooling cycles due to bimetallic effect, then the substrate conforms to the base plate contour during soldering, but cooling causes warping return and local gap increase leading to vacuum and cavity formation
Solution Approach 1:
The non-solderable coating is applied in advance to regions where cavities are likely to form during the soldering process. This preliminary action prevents the harmful effect of vacuum formation and cavity creation that would otherwise occur due to substrate warping and cooling. By pre-marking these areas as non-solderable, the invention counteracts the natural tendency of the system to form defects during thermal cycling.
3Quantity of substance
If solder is allowed to fill all areas during system soldering, then complete metallurgical bonding is achieved, but vacuum formation in inner areas leads to cavity formation that reduces performance and lifetime
Solution Approach 1:
The invention creates local quality differentiation by applying non-solderable coatings to specific regions of the metal layer. This ensures that solder fills only the areas where it is needed (under power semiconductor elements for electrical and thermal connection) while preventing solder accumulation in areas where it would create cavities and vacuum. The result is optimized solder distribution that maximizes reliability while minimizing defect formation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances heat transfer and increases the reliability and performance of power semiconductor assemblies by minimizing voids and improving thermal conductivity.
Implementation Method 1
Due to the different materials with varying coefficients of thermal expansion, a bimetallic effect occurs in the substrate, causing it to warp with temperature changes.
Implementation Method 2
The process of creating this bond by soldering is called system soldering. During this process, the materials involved (base plate, solder, power substrate) are heated until the solder reaches its melting point.
Implementation Method 3
Within this cavity, there is no continuous, metallurgical bond between the power substrate and the base plate, thus locally reducing heat transfer from the power semiconductor to the base plate.
Data Source
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AI summary
The invention relates to a power semiconductor arrangement (2) comprising at least one power semiconductor element (4), a substrate (6) comprising a dielectric material layer (8) with a first surface (10) and a second surface (12) which is arranged on a side of the dielectric material layer (8) facing away from the first surface (10), a conductive structure (14) which is formed on the first surface (10) of the dielectric material layer (8) and on which the at least one power semiconductor element (4) is contacted, and a metal layer (16) which is arranged on the second surface (12) of the dielectric material layer (8).To improve the performance and reliability of a power semiconductor arrangement, it is proposed that the metal layer (16) has at least one recess (22) and/or at least one non-solderable coating (40) which is arranged in a top view outside a contact surface (20) of the at least one power semiconductor element (4).