Power Supply Circuit Ripple Suppression via Dynamic Comparator Modes
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Solution Overview
Problem
Existing power supply circuits for semiconductor devices face challenges in generating stable output voltage as the ripple component increases with output current, particularly due to slow comparator speed when the output voltage falls below the reference voltage.
Innovation Solution
A power supply circuit that includes a comparison unit comparing the divided voltage with multiple reference voltages, a selector selecting one of the reference voltages based on the comparison result, and a booster circuit controlling the clock signal to boost the output voltage, thereby partially overlapping ripple rising and falling components to suppress overall ripple.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the comparator speed is controlled to be slow when the divided voltage falls below the reference voltage, then the ripple component is suppressed when output current is small, but the ripple component becomes larger when output current is large
Solution Approach 1:
The patent applies dynamics by making the comparator speed adjustable based on operating conditions. The comparator includes a first operation mode for small output currents with slower comparison speed to suppress ripple, and a second operation mode for large output currents with faster comparison speed to maintain stability. This dynamic switching resolves the contradiction between ripple suppression and response speed.
Solution Approach 2:
The patent changes the comparator's operational parameters (speed) based on the output current magnitude. When output current is small, the comparator operates in a first mode with optimized ripple suppression characteristics. When output current is large, it switches to a second mode with faster response. This parameter change allows the system to optimize performance for different operating conditions.
2Reliability
If the comparator speed is increased to maintain stability when output current is large, then the ripple component is reduced, but the output voltage fluctuation increases when output current is small
Solution Approach 1:
The patent uses dynamic operation modes in the comparator to adapt to different output current conditions. In the first operation mode (small current), the comparator is configured to minimize ripple. In the second operation mode (large current), it prioritizes fast response for stability. This dynamic adaptation resolves the contradiction between ripple suppression and stability maintenance.
Solution Approach 2:
The comparator's internal parameters are changed based on operating conditions through the operation mode switching mechanism. This allows optimization of the comparison process for either ripple suppression or fast response depending on the current level, eliminating the need to compromise between these conflicting requirements.
3Device complexity
If a single reference voltage is used in the comparison unit, then the device complexity is reduced, but the ripple suppression effectiveness decreases
Solution Approach 1:
The patent segments the reference voltage function into multiple operation modes within the comparator. Instead of using a single reference voltage, the system divides the comparison process into first and second operation modes, each optimized for different current conditions. This segmentation allows sophisticated ripple suppression without proportionally increasing overall system complexity.
Solution Approach 2:
The comparator is designed with multi-functionality, serving both ripple suppression and fast response functions through its dual operation modes. This universal design allows a single component to handle multiple operational requirements, avoiding the need for separate circuits for different current conditions.
Data Source
AI summary
A power supply circuit capable of generating a stable output voltage is provided. According to one embodiment, the power supply circuit includes a comparison unit that compares the divided voltage corresponding to the external output voltage with each of the first reference voltage and the second reference voltage to output the comparison result, a NAND circuit that controls whether or not to output the clock signal based on the comparison result by the comparison unit, and a booster circuit that boosts the external output voltage when the clock signal is supplied via the NAND circuit.