Power Supply Control for Image Processors Using Time-Based Memory Segmentation
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Solution Overview
Problem
Existing image processing and image forming apparatuses face challenges in efficiently managing power consumption during idle periods, as they transition to a power-saving state, which can lead to data storage delays and increased complexity due to the need for adequate buffer sizes and PLL circuit operation.
Innovation Solution
A power supplying control apparatus with a transition unit and determining unit, which includes a reference signal generator, memory control units, and a communication line network control unit, determines the transition to power-supplied or power-shutoff states based on time periods and communication network conditions, allowing the PLL circuit to be shut off or maintained during sleep mode to optimize power saving without compromising data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the apparatus transitions to a power-saving state by shutting off power to the PLL circuit and memory control unit, then power consumption is reduced, but data storage delays occur and the system cannot handle incoming communication data properly
Solution Approach 1:
The memory system is segmented into two distinct memory units: a first memory (main memory) and a second memory (buffer memory). This segmentation allows the system to shut off power to the main memory while maintaining a smaller buffer memory operational, enabling data to be temporarily stored during transitions without requiring the entire memory system to remain powered.
Solution Approach 2:
The determining unit calculates time periods in advance before power transition occurs. The first time period is calculated based on buffer memory capacity and communication speed, representing the maximum time data can be buffered. The second time period is calculated based on main memory access speed. This preliminary calculation allows the system to proactively manage data transfer timing, ensuring data is moved to main memory before power is shut off, thus preventing data loss.
2Reliability
If the buffer memory capacity is increased to handle data during power-saving transitions, then data storage reliability improves, but device complexity and cost increase
Solution Approach 1:
Instead of providing buffer memory capacity for all possible scenarios, the system calculates the minimum necessary buffer capacity based on the product of communication line speed and the first time period. This partial action approach provides sufficient buffering for normal operating conditions while avoiding the excessive complexity and cost of oversized buffer memory.
Solution Approach 2:
The system dynamically adjusts operational parameters including buffer memory capacity, first time period, and second time period based on communication speed and memory access characteristics. By changing these parameters adaptively rather than using fixed large values, the system achieves reliable data storage with optimized rather than excessive buffer capacity.
3Speed
If the apparatus maintains PLL circuit operation during sleep mode to enable quick recovery, then system recovery speed improves, but power consumption increases
Solution Approach 1:
The PLL circuit operates in a periodic manner: fully operational during active states, shut off during power-saving states, and rapidly restarted when needed. The determining unit calculates whether to maintain PLL operation based on whether the current time exceeds the second time period. This periodic operation allows the system to balance power consumption with recovery speed requirements.
Solution Approach 2:
The system dynamically adjusts PLL circuit operation based on real-time conditions. The transition unit and determining unit work together to decide whether to maintain or shut off PLL power based on the calculated time periods and current system state. This dynamic approach allows optimal power-saving behavior when quick recovery is not needed, while enabling rapid recovery when data storage requirements demand it.
Data Source
AI summary
A power supplying control apparatus includes a transition unit that causes a control apparatus to transition to one of a power supplied state that causes power to be supplied and a power shutoff state that shuts off the supplying of power, and a determining unit that determines a transition target of the transition unit in accordance with a first time period and a second time period, the first time period having a length of time beyond which no further memory space is available from a second memory, and thus being determined by a transmission and reception speed of information to a communication line network and a storage capacity of the second memory, the second time period being so long as to enable information stored on the second memory to be stored on a first memory in the power shutoff state.