Power Supply Controller Overvoltage Protection
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Solution Overview
Problem
In DC/DC converters, when an abnormality occurs at the external terminal, such as being opened, the feedback voltage becomes ground potential, leading to an overvoltage applied to subsequent circuits due to maximum PWM duty, which is not effectively protected by existing technologies.
Innovation Solution
A power supply controller with a feedback control unit generating pulse-shaped PWM signals, a low voltage detection unit, and a selection unit that chooses between high and low duty clock signals based on feedback voltage, incorporating a reset signal generation unit and PWM signal generation using an AND circuit, error amplifier, slope generation, and soft start to manage PWM duty and prevent overvoltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage dividing resistors are built in the IC to generate feedback voltage, then the output voltage can be stabilized under normal conditions, but when the external terminal is opened, the feedback voltage becomes ground potential causing maximum PWM duty and overvoltage that damages subsequent circuits
Solution Approach 1:
The patent applies preliminary action by detecting the abnormal state (open terminal) before overvoltage damages occur. The low voltage detection unit monitors the feedback voltage and identifies when it drops to ground potential, triggering the selection unit to switch to the second clock signal with low duty cycle, thereby preventing overvoltage damage before it happens.
Solution Approach 2:
The patent introduces an intermediary mechanism (the selection unit and low voltage detection unit) that mediates between the feedback control unit and the PWM signal generation. When abnormality is detected, this intermediary switches the clock signal duty cycle, preventing the direct transmission of maximum duty cycle signals that would cause overvoltage, thus protecting subsequent circuits.
2Ease of operation
If the feedback voltage is used directly for PWM control, then the control is simple and responsive, but it cannot distinguish between normal low voltage states and abnormal open terminal states
Solution Approach 1:
The patent segments the control function into two independent pathways: the feedback control unit that handles normal voltage regulation, and the low voltage detection unit that handles abnormality detection. This segmentation allows the system to maintain simple feedback control while adding reliable abnormality detection capability through a separate monitoring channel.
Solution Approach 2:
The low voltage detection unit acts as an intermediary that monitors the feedback voltage without interfering with the normal feedback control operation. It provides abnormality detection information to the selection unit, enabling the system to distinguish between normal and abnormal states while maintaining the simplicity of the original feedback control mechanism.
Data Source
AI summary
A power supply controller used in a DC/DC converter includes a feedback control unit that generates a pulse-shaped PWM signal having a first level that is one of a high level and a low level and a second level that is the other of the high level and the low level, on the basis of a feedback voltage based on an output voltage of the DC/DC converter; a low voltage detection unit that detects a low voltage of the feedback voltage; and a selection unit that chooses, as a chosen clock signal, a first clock signal having a high duty when the low voltage is not detected by the low voltage detection unit, and chooses a second clock signal having a low duty when the low voltage is detected by the low voltage detection unit. The feedback control unit includes a reset signal generation unit that generates a pulse-shaped reset signal having the first level and the second level, based on the feedback voltage, and a PWM signal generation unit that generates the PWM signal at the first level during a period that is an overlap between a period during which the reset signal is at the first level and a period during which the chosen clock signal is at the first level.