Power Supply Enable Circuit with NAND Gate and Delay Logic
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Solution Overview
Problem
Existing power supply circuits cannot activate the main system of an electronic device when connected to an external power supply, limiting their functionality and efficiency.
Innovation Solution
A power supply enable circuit is designed with a multi-input NAND gate and a delay circuit, connected to activation signal sources, allowing the circuit to activate the main system when any activation signal is logic 0, and includes additional components like NOT gates, AND gates, resistors, and a switch circuit for flexible power management and reset functions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the power supply circuit is powered off to minimize power consumption when the main system is shut down, then power consumption is reduced, but the circuit cannot activate the main system when connected to an external power supply
Solution Approach 1:
The power supply enable circuit is configured to be activated by external power supply connection before the main system is fully powered on. The circuit monitors the enable input terminal and automatically generates an activation signal when external power is detected, allowing the main system to be activated without requiring the power supply circuit to remain continuously powered.
Solution Approach 2:
The power supply enable circuit acts as an intermediary between the external power supply and the main system. It receives the enable input signal, processes it through logical operations (NAND gate and delay circuit), and generates the appropriate activation signal to trigger the main system, thereby mediating the activation process without requiring continuous power consumption.
2Adaptability or versatility
If the power supply circuit is kept active to enable main system activation when external power is plugged in, then activation capability is improved, but power consumption increases
Solution Approach 1:
The power supply enable circuit operates in a periodic manner by monitoring the enable input terminal intermittently rather than remaining continuously active. The delay circuit introduces a time delay to generate activation signals only when necessary, allowing the circuit to consume minimal power during monitoring phases and activate only when external power is detected, thus reducing overall power consumption while maintaining activation capability.
3Adaptability or versatility
If a complex power supply enable circuit is designed to provide flexible power management and reset functions, then functionality is improved, but circuit complexity increases
Solution Approach 1:
The power supply enable circuit is segmented into distinct functional modules: an enable input terminal for signal reception, a NAND gate for logical processing, a delay circuit for timing control, and an output terminal for signal generation. This segmentation allows each component to perform a specific function, providing flexible power management and reset capabilities while keeping the overall circuit structure organized and manageable.
Solution Approach 2:
The power supply enable circuit is designed to perform multiple functions using a unified structure. The same circuit configuration can provide both power management functionality (activating the main system when external power is detected) and reset functionality (controlling the reset signal through the enable input). This multi-functionality reduces the need for separate dedicated circuits, thereby limiting the increase in overall circuit complexity while enhancing versatility.
Data Source
AI summary
Disclosed is a power supply enable circuit. The power supply enable circuit includes a multi-input NAND gate, input terminals of the multi-input NAND gate respectively connected to a plurality of activation signal sources; and a delay circuit, an input terminal of the delay circuit electrically connected to a shared activation signal source of the plurality of activation signal sources. An output terminal of the delay circuit is electrically connected to an enable input terminal of a power supply circuit after performing a logical AND with an output terminal of the multi-input NAND gate.