Power Supply Gate Clamp Circuit for Rush Voltage Suppression
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Solution Overview
Problem
In power supply circuits, reducing the resistance value of a pull-down resistor to manage steep changes in input voltage leads to increased power consumption, as it results in higher current flow during rush voltage events.
Innovation Solution
A switch circuit with an NMOS transistor and a voltage holding circuit, utilizing a capacitor to transmit rush voltage and diodes or Zener diodes to maintain a voltage higher than the threshold for the transistor, preventing the transistor from turning on during rush events and thus reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resistance value of the pull-down resistor is reduced to cope with steep changes in rush voltage, then the ability to suppress gate voltage increase is improved, but power consumption increases
Solution Approach 1:
The patent replaces the static pull-down resistor with a dynamic switch circuit using an NMOS transistor that can change its resistance state between on and off based on control signals. This allows the system to have low resistance (high current capability) only when needed to suppress gate voltage increase during rush events, and high resistance (low current) during normal operation, thus resolving the contradiction between reliability and power consumption
Solution Approach 2:
The switch circuit operates periodically or event-driven based on detection of rush voltage conditions. The control signal activates the NMOS transistor only during rush events (steep changes in input voltage) rather than continuously, enabling the system to suppress gate voltage increase when needed while minimizing power consumption during normal operation
2Reliability
If a pull-down resistor is used to prevent rush current, then the ability to suppress large current flow is improved, but power consumption increases due to continuous current flow
Solution Approach 1:
The static pull-down resistor is replaced with a dynamic NMOS transistor switch that can dynamically adjust its resistance. During rush events, the transistor turns on to provide low resistance and suppress rush current. During normal operation, the transistor turns off to eliminate continuous current flow, thus maintaining rush current suppression capability while dramatically reducing energy loss
Solution Approach 2:
The patent extracts the rush current suppression function from the continuous operation mode and separates it into an event-driven mode. The switch circuit is activated only when rush conditions are detected, taking out the harmful continuous current flow from the system while preserving the beneficial rush current suppression capability when actually needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively prevents large currents from flowing to the load during rush voltage occurrences at high slew rates without increasing power consumption, ensuring reliable operation and preventing malfunctions.
Implementation Method 1
a capacitor connected between an input end of the power supply voltage and a gate of the second transistor
Implementation Method 2
utilizing a capacitor to transmit rush voltage and diodes or Zener diodes to maintain a voltage higher than the threshold for the transistor
Data Source
AI summary
A power supply circuit in an embodiment includes a first transistor that supplies an output based on an input power supply voltage to a load or stops the supply of the output to the load, a second transistor, one end of a current path of which is connected to the gate of the first transistor and another end of the current path of which is connected to a reference potential point, the second transistor being turned on and off according to a level of a gate voltage of the second transistor, a capacitor connected between an input end of the power supply voltage and a gate of the second transistor, and a voltage holding circuit connected between the gate of the second transistor and the reference potential point and configured to hold the gate voltage of the second transistor.