Power Supply Hardware Interlock for Dynamic Mode Switching
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Solution Overview
Problem
Digital circuits face inefficiencies and performance issues due to power supply disruptions when current demand suddenly increases, as existing power supply configurations often operate in high current modes even when lower current modes are sufficient, leading to excess capacity and reduced efficiency.
Innovation Solution
Implementing a hardware interlock to govern power demand in lower capacity modes, allowing dynamic switching to higher capacity modes when necessary, and disabling the interlock once the higher mode is achieved to prevent power demand from exceeding the lower capacity mode's limits, thereby optimizing power supply configuration based on current demand.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the power supply operates in high current mode to avoid performance issues due to power supply disruptions, then reliability is improved, but efficiency deteriorates due to excess capacity
Solution Approach 1:
The power supply configuration is made dynamic by introducing a hardware interlock that enables real-time switching between high current mode and low current mode based on actual circuit demands. The interlock detects when the circuit is in sleep mode and automatically switches the power supply to low current mode, then switches back to high current mode when wake mode is detected, allowing the system to adapt its power delivery characteristics to match actual needs rather than operating statically in high current mode
2Loss of energy
If the power supply switches to low current mode to increase efficiency, then energy loss is reduced, but reliability deteriorates due to potential power supply disruptions when current demand increases
Solution Approach 1:
The hardware interlock implements preliminary anti-action by proactively switching the power supply to high current mode before the circuit can demand excessive current that would exceed low current mode capabilities. The interlock detects sleep mode conditions and preemptively transitions the power supply to low current mode, preventing potential disruptions before they occur. When wake mode is detected, it preemptively switches back to high current mode, ensuring power availability is maintained before demand increases
3Loss of energy
If the power supply operates in low current mode when circuit current demand is within specifications, then efficiency is improved, but adaptability deteriorates when the circuit subsequently demands higher current levels
Solution Approach 1:
The hardware interlock implements feedback by continuously monitoring the circuit's operational state (sleep mode vs. wake mode) and using this information to automatically adjust the power supply configuration. When the interlock detects that the circuit has transitioned from sleep mode to wake mode, it receives feedback about the changed current demand requirements and automatically switches the power supply from low current mode to high current mode, ensuring the power supply adapts to actual circuit needs
Data Source
AI summary
Circuits, systems, and methods for dynamically controlling a power supply configuration in response to load requirements from a digital circuit are disclosed. To increase efficiency, the power supply is configurable to be switched into a lower capacity mode. To prevent the digital circuit from demanding capacity beyond the lower capacity mode of the power supply before the power supply can be switched into a higher capacity mode, at least one hardware interlock is employed. The hardware interlock(s) governs the power demand of the digital circuit from extending beyond the lower capacity mode of the power supply. If it is detected that the hardware interlock(s) limits power demand in the digital circuit beyond a power demand threshold, the power supply can be switched to the higher capacity mode. The hardware interlock(s) can then be disabled. In this manner, the power supply can dynamically provide increased capacity as demanded by the dynamic performance of the digital circuit.