Power Supply Network Evaluation Before Chip Physical Implementation
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Solution Overview
Problem
Conventional power supply solution evaluation methods require physical implementation first, followed by evaluation, leading to lengthy design cycles and reliance on incomplete chip design data, which affects the chip design cycle significantly.
Innovation Solution
A method and apparatus for evaluating power supply designs by determining a power supply network, generating an electrical configuration associated with predetermined power consumption, and predicting voltage losses to assess the network's integrity before physical implementation, allowing for early-stage evaluation and rapid iteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If physical implementation is performed first followed by evaluation, then evaluation accuracy is improved, but design cycle time increases significantly
Solution Approach 1:
The patent performs power supply evaluation before physical implementation by using extracted layout information and electrical configuration data to simulate and predict voltage drops and power supply integrity. This preliminary evaluation allows designers to identify and fix issues in the design stage without waiting for physical implementation, thereby reducing design cycle time while maintaining sufficient evaluation accuracy.
Solution Approach 2:
The patent creates a virtual model of the power supply network by extracting layout information from GDS files and generating electrical configuration data. This digital copy enables evaluation without physical implementation, allowing multiple iterations of evaluation and optimization before fabrication, thus significantly reducing the design cycle while providing accurate enough predictions for design decision-making.
2Reliability
If complete chip design data is available for evaluation, then evaluation reliability is improved, but design iteration speed decreases
Solution Approach 1:
The patent uses partial chip design data (layout information from GDS files and electrical configuration) rather than waiting for complete design data. This partial information is sufficient to extract power supply network topology and perform meaningful evaluation of voltage drops and power supply integrity, enabling early-stage evaluation and rapid iteration without compromising evaluation reliability for design decisions.
Solution Approach 2:
The patent performs evaluation at an early stage when only partial design data is available, rather than waiting for complete design data. By extracting power supply network information from available layout data and performing preliminary evaluation, the system enables rapid design iteration while maintaining sufficient evaluation reliability to guide design optimizations.
Data Source
AI summary
According to embodiments of the disclosure, there are provided a method, an apparatus, a device, and a storage medium for evaluating a power supply design. The method includes determining a power supply network designed for a chip, the power supply network comprising a plurality of power supply lines for power transmission and indicating a position and a pattern of each of the plurality of power supply lines in the chip. The method includes generating, for the power supply network, an electrical configuration at least associated with a predetermined power consumption of the chip. The method includes determining predicted voltage losses at different positions of the power supply network with the electrical configuration. In this way, fast evaluation and verification of the power supply solution can be implemented, which is beneficial to shorten the cycle of the chip design.