Power Supply Hold-Up Circuit With Surge Current Suppression
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Solution Overview
Problem
Existing power supply systems for communication devices face challenges in suppressing surge currents caused by overshoot of input voltage or current, leading to increased costs due to the need for large Safe Operating Area (SOA) FETs and reduced performance and reliability.
Innovation Solution
The introduction of a current suppression circuit in the power supply assisting sub-system, which includes a third transistor that can be turned off to suppress current flowing through the second transistor when the current exceeds a preset Over-Current (OC) threshold, and the use of smaller SOA FETs to reduce costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a holdup capacitor with larger capacitance is introduced to suppress oscillation and supply power when power source is temporarily off, then the power supply stability is improved, but a surge current is caused in the power supply system
Solution Approach 1:
A current suppression circuit is introduced as an intermediary component between the power source and the load circuit. This circuit includes a current suppression transistor that acts as a mediator to control and limit the charging current to the holdup capacitor, preventing surge current while maintaining the capacitor's ability to suppress oscillation and provide backup power.
Solution Approach 2:
The invention dynamically changes the electrical parameters (current limiting characteristics) of the power supply system by introducing a current suppression transistor. This transistor adjusts the charging current parameters to prevent excessive current spikes while still allowing sufficient current to charge the holdup capacitor for its intended functions.
2Object-affected harmful factors
If large Safe Operating Area (SOA) FETs are used to handle surge current, then the surge current suppression capability is improved, but the cost increases
Solution Approach 1:
The current suppression function is segmented from the main power FETs and implemented by a dedicated current suppression transistor in the current suppression circuit. This segmentation allows the use of smaller, less expensive SOA FETs for the main power path while the current suppression transistor handles the surge current limitation function.
Solution Approach 2:
The current suppression transistor serves as an intermediary device that protects the main power FETs from surge current. By placing this transistor in series with the holdup capacitor charging path, it limits the maximum current that can flow through the system, allowing cheaper FETs to be used in the main power circuit.
3Reliability
If the current suppression transistor is turned off to suppress current flowing through the second transistor when current exceeds OC threshold, then the over-current protection is improved, but the power supply to load circuit may be affected
Solution Approach 1:
The control logic continuously monitors the current flowing through the second transistor and provides feedback control. When the current exceeds the preset Over-Current threshold, the control logic turns off the current suppression transistor to block excessive current. The system maintains power supply continuity by switching to alternative power paths or adjusting operating parameters when normal operation is restored.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively suppresses surge currents during both power-on and normal operation periods, allows the use of smaller SOA FETs to reduce costs, and enhances the reliability of Over-Voltage Protection (OVP) and Over-Current Protection (OCP) functions.
Implementation Method 1
a first transistor, having a control terminal, a first terminal connected to the second node via a first resistor, and a second terminal, as the first port, connected to the second electrode of the first capacitor; the first transistor being configured to be turned on by a control signal at the control terminal of the first transistor to charge the first capacitor
Implementation Method 2
a second transistor, having a control terminal, a first terminal connected to the second node via a second resistor, and a second terminal, as the second port, connected to the load circuit; the second transistor being configured to be turned on by a control signal at the control terminal of the second transistor to supply power to the load circuit
Implementation Method 3
a third transistor, having a control terminal, a first terminal connected to the second terminal of the second transistor, and a second terminal connected to the second electrode of the first capacitor; the third transistor being configured to be turned off by a control signal at the control terminal of the third transistor to suppress a current flowing through the second transistor
Implementation Method 4
configured to suppress oscillation caused by load variation of a load circuit that is connected between the first node and the second circuit, and to supply power to the load circuit when the power source is temporarily off
Data Source
AI summary
The present disclosure provides a power supply system, including: a power source connected between a first node and a second node for applying an input voltage; a first circuit, connected between the first node and a second circuit; and configured to suppress oscillation caused by load variation of a load circuit that is connected between the first node and the second circuit, and to supply power to the load circuit when the power source is temporarily off; the second circuit, having a first port connected to the first circuit, a second port connected to the load circuit, and a third port connected to the second node; and configured to charge the first circuit and supply power to the load circuit; and a third circuit, connected between the first circuit and the load circuit; and configured to suppress a current flowing into the second circuit.