Power Supply Tracking Circuitry for Memory Timing Alignment
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Solution Overview
Problem
Dual-rail memory systems face data loss and performance degradation due to timing misalignment of control signals across different power supply domains, leading to excess power dissipation and data corruption.
Innovation Solution
A tracking circuitry that aligns the falling edges of data clock signals with those of the write and wordline signals using level shifters, inverters, and NOR gates, allowing clock signals to operate at the lower power supply voltage of the control circuitry while aligning with the timing of bitcells operating at a higher power supply voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory bitcells operate at a higher power supply voltage for optimal performance, then memory performance is improved, but control signals from lower voltage control circuitry become misaligned in timing
Solution Approach 1:
A tracking circuit acts as an intermediary between the control circuitry operating at a first power supply voltage and the memory bitcells operating at a second power supply voltage. The tracking circuit receives clock signals from the control circuitry and generates adjusted clock signals that are synchronized with the higher voltage domain, ensuring proper timing alignment without requiring the control circuitry to operate at higher voltages.
Solution Approach 2:
The tracking circuit dynamically adjusts parameters of clock signals including voltage level, phase, and timing based on the power supply voltage difference between domains. By monitoring the power supply voltage and modifying clock signal characteristics accordingly, the system maintains timing synchronization across different voltage domains despite varying operating conditions.
2Loss of energy
If clock signals are generated at the lower power supply voltage of control circuitry, then power consumption is reduced, but timing alignment with higher voltage memory operations becomes difficult
Solution Approach 1:
The tracking circuit serves as a mediator that receives clock signals from the lower voltage control circuitry and transforms them into properly timed signals for the higher voltage memory domain. This allows the control circuitry to operate efficiently at lower voltages while still achieving precise timing synchronization with memory operations through the voltage and timing transformation performed by the tracking circuit.
3Loss of energy
If dual rail memory devices use different power supply voltages for memory and control circuitry, then power efficiency is improved, but data loss and corruption occur due to timing misalignment
Solution Approach 1:
The tracking circuit implements feedback mechanisms by monitoring the power supply voltage levels and using this information to dynamically adjust clock signal timing and voltage characteristics. This feedback loop ensures that clock signals remain synchronized with memory operations despite voltage differences, preventing data loss and corruption while maintaining the power efficiency benefits of dual-rail architecture.
Solution Approach 2:
The tracking circuit acts as an intermediary that bridges the voltage domain gap between control circuitry and memory bitcells. By transforming clock signals from the control circuitry's voltage domain to the memory's voltage domain with proper timing adjustment, it enables reliable data transfer and prevents corruption that would otherwise occur due to timing misalignment.
Data Source
AI summary
Tracking circuitry for a memory device is disclosed. The tracking circuitry includes an inverter, a level shifter, delay circuitry, and a logic gate. The inverter is configured to receive a first clock signal and generate an inverted clock signal. The level shifter is configured to receive the first clock signal and the inverted clock signal and generate a level shifted clock signal. The delay circuitry is configured to receive the level shifted clock signal and generate an inverted level shifted clock signal. The logic gate comprises a first input configured to receive the first clock signal and a second input configured to receive the inverted level shifted clock signal. The logic gate is configured to generate a second clock signal based on the first clock signal and the inverted level shifted clock signal.