Power Switch Arbiter Sequences Domain Activation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In System-on-a-Chip (SoC) designs, the simultaneous powering up of multiple power domains can cause a reduction in the supply voltage level due to excessive instantaneous electrical current, leading to potential failures and inefficiencies in power management.
Innovation Solution
A power switch arbiter is implemented to arbitrate and sequence the powering up of different power domains, limiting the simultaneous power up to avoid voltage drops by considering the instantaneous electrical current draw and credit management, allowing domains to power up at non-restricted or restricted rates based on available credits and voltage supply constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple power domains are powered up simultaneously to reduce turn-on delay, then the activation speed is improved, but the supply voltage level drops below the minimum allowable level due to excessive instantaneous current
Solution Approach 1:
The power switch arbiter performs preliminary assessment of instantaneous current draw requirements before allowing power domains to activate. The system evaluates the sum of instantaneous currents that would be drawn if multiple domains activate simultaneously, and only permits activation sequences that will not cause the supply voltage to drop below the minimum threshold. This preliminary checking mechanism enables faster activation while preventing voltage sags.
2Reliability
If the system is designed to handle worst-case simultaneous power up scenarios, then the supply voltage stability is ensured, but the layout becomes overly conservative and inefficient
Solution Approach 1:
Instead of designing for the static worst-case scenario where all power domains activate simultaneously, the system dynamically sequences power domain activations based on real-time current draw assessments. The power switch arbiter adaptively determines which domains can activate together and which must be staggered, optimizing the activation sequence for each situation rather than preparing for the maximum possible load at all times. This dynamic approach reduces layout complexity while maintaining voltage stability.
3Reliability
If power domains are sequenced to limit instantaneous current draw, then the supply voltage stability is maintained, but the turn-on delay increases
Solution Approach 1:
The system changes the parameter of activation timing based on the assessed current draw requirements. Power domains with lower instantaneous current requirements are permitted to activate simultaneously and earlier, while domains with higher current requirements are sequenced to activate after lower-current domains have stabilized. This parameter-based sequencing minimizes the total activation time while ensuring that the sum of simultaneous current draws never exceeds the supply voltage threshold.
Data Source
AI summary
An arbitrator governs an arbitration between different power domains and sequences powering up the different power domains supplied by the same voltage supply (VS) circuit on the Chip. The arbitrator has sequencing logic that limits how many different power domains simultaneously power up to a maximum amount, which is less than enough instantaneous electrical current drawn on the VS-circuit to cause a reduction below a minimum allowable supply voltage level for the VS-circuit. The sequencing logic manages the sequencing of powering up the different power domains by factoring in i) whether different power domains arbitrating to power up are part of a set of power domains that share the VS-circuit, ii) an amount of an instantaneous electrical current drawn, and iii) an amount of credits available before the minimum allowable supply voltage level occurs for that VS-circuit. The sequencing logic controls a behavior of the power domains when powering up from multiple different behaviors.