Power Switch Layout in Semiconductor Circuits for Higher Supply Capacity
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Solution Overview
Problem
Conventional semiconductor devices face a reduction in power supply capacity due to the need for larger power switch circuits, which increases the size of the vacant area and subsequently reduces the size of logic circuits, leading to increased chip size and decreased integration.
Innovation Solution
The implementation of additional transistors in the vacant areas of power switch circuits, matching the size of transistors in logic circuits, enhances power supply capacity without increasing the layout area by alleviating shape variation and electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power switch circuits are provided between power line and virtual power line to reduce leakage current, then leakage current is reduced, but the size of power switch circuits increases leading to reduced logic circuit area
Solution Approach 1:
The power switch circuit is divided into two separate transistors: a first transistor connected to the power line and virtual power line, and a second transistor connected to the functional circuit. This segmentation allows each transistor to be optimized independently, with the first transistor being larger for better leakage control and the second transistor being smaller to save area for logic circuits.
Solution Approach 2:
Different transistors in the power switch circuit are given different sizes based on their specific functions. The first transistor is made larger to effectively control leakage current on the power line, while the second transistor is made smaller since it only needs to control power to the functional circuit, thereby reducing the overall area requirement.
2Power
If larger power switch circuits are provided to improve power supply capacity, then power supply capacity is improved, but the vacant area increases leading to reduced integration
Solution Approach 1:
The power switch circuit is segmented into two transistors with different sizes, allowing the first transistor to provide sufficient power supply capacity while the second transistor minimizes area occupation. This enables adequate power delivery without proportionally increasing the total circuit area, thus maintaining integration density.
Solution Approach 2:
The transistor sizes are optimized by changing the parameter of width-to-length ratio. The first transistor has a larger ratio for higher current capacity, while the second has a smaller ratio for area efficiency. This parameter optimization allows the circuit to achieve both sufficient power supply capacity and high integration.
Data Source
AI summary
A semiconductor device includes a first area including a logic circuit, a second area including a functional circuit, a first power line, a second power line that supplies a power to the logic circuit and the functional circuit, and a first power switch circuit connected to the first power line and the second power line, wherein the first power switch circuit includes a first transistor larger than a transistor provided in the logic circuit and being connected to the first power line and the second power line, an end cap provided in an area next to the functional circuit, and a second transistor provided between the end cap and an area including the first transistor, the second transistor being of a same size as the transistor provided in the logic circuit and being connected to the first power line and the second power line.